PIC16F193X Datasheet, PDF (288/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
22.3.8 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in Slave mode
• from Idle, in Slave or Master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
TABLE 22-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
APFCON
—
CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE
PIR1
TMR1GIf
ADIF
RCIF
TXIF
SSPIF
CCP1IF
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1
WCOL
SSPOV SSPEN
CKP
SSPM3 SSPM2
SSPCON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT SBCDE
SSPSTAT
TRISA
SMP
TRISA7
CKE
TRISA6
D/A
TRISA5
P
TRISA4
S
TRISA3
R/W
TRISA2
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2
Legend: Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.
Bit 1
SSSEL
INTF
TMR2IE
TMR2IF
SSPM1
AHEN
UA
TRISA1
TRISC1
Bit 0
CCP2SEL
IOCIF
TMR1IE
TMR1IF
SSPM0
DHEN
BF
TRISA0
TRISC0
Register
on Page
84
73
74
77
281*
277
279
276
86
94
DS41364A-page 286
Preliminary
© 2008 Microchip Technology Inc.