PIC16F193X Datasheet, PDF (186/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
19.1 Capture/Compare/PWM
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate a Pulse-Width Modulated signal of
varying frequency and duty cycle.
Table 19-1 shows the timer resources required by the
CCP module.
TABLE 19-1: REQUIRED TIMER
RESOURCES
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2 or 4 or 6
REGISTER 19-1: CCPXCON: CCPX CONTROL REGISTER
R/W-00
PxM1⁽¹⁾
bit 7
R/W-0/0
PxM0⁽¹⁾
R/W-0/0
DCxB1
R/W-0/0
DCxB0
R/W-0/0
CCPxM3
R/W-0/0
CCPxM2
R/W-0/0
CCPxM1
R/W-0/0
CCPxM0
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
bit 7-6
bit 5-4
bit 3-0
PxM<1:0>: Enhanced PWM Output Configuration bits⁽¹⁾
If CCPxM<3:2> = 00, 01, 10:
xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins
If CCPxM<3:2> = 11:
00 =
01 =
10 =
11 =
Single output; PxA modulated; PxB, PxC, PxD assigned as port pins
Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
CCPxM<3:0>: ECCPx Mode Select bits
0000 =
0001 =
0010 =
0011 =
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
Capture/Compare/PWM off (resets ECCPx module)
Reserved
Compare mode: toggle output on match
Capture mode
Capture mode: every falling edge
Capture mode: every rising edge
Capture mode: every 4th rising edge
Capture mode: every 16th rising edge
Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2
trigger also starts A/D conversion if A/D module is enabled)⁽¹⁾
CCP<5:4> only:
11xx = PWM mode
ECCP<3:1> only:
1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high
1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low
1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high
1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low
Note 1: These bits are not implemented on CCP<5:4>.
DS41364A-page 184
Preliminary
© 2008 Microchip Technology Inc.