PIC16F193X Datasheet, PDF (124/418 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F193X/LF193X
TABLE 9-1:
SRCLK
111
110
101
100
011
010
001
000
SRCLK FREQUENCY TABLE
Divider FOSC = 32 MHz FOSC = 20 MHz
512
62.5 kHz
39.0 kHz
256
125 kHz
78.1 kHz
128
250 kHz
156 kHz
64
500 kHz
313 kHz
32
1 MHz
625 kHz
16
2 MHz
1.25 MHz
8
4 MHz
2.5 MHz
4
8 MHz
5 MHz
FOSC = 16 MHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
FOSC = 4 MHz
7.81 kHz
15.6 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
FOSC = 1 MHz
1.95 kHz
3.90 kHz
7.81 kHz
15.6 kHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
REGISTER 9-1: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0
SRLEN
bit 7
R/W-0/0
SRCLK2
R/W-0/0
SRCLK1
R/W-0/0
SRCLK0
R/W-0/0
SRQEN
R/W-0/0
SRNQEN
R/S-0/0
SRPS
R/S-0/0
SRPR
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only -
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
SRLEN: SR Latch Enable bit
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock
001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock
010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock
011 = Generates a 1 FOSC wide pulse every 32th FOSC cycle clock
100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock
101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock
110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock
111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1 = Q is present on the SRQ pin
0 = Q is internal only
If SRLEN = 0:
SR latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1 = Q is present on the SRnQ pin
0 = Q is internal only
If SRLEN = 0:
SR latch is disabled
SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse input for 1 Q-clock period
0 = Do not generate pulse. Always reads back ‘0’.
SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse input for 1 Q-clock period
0 = Do not generate pulse. Always reads back ‘0’.
DS41364A-page 122
Preliminary
© 2008 Microchip Technology Inc.