LAN9500 Datasheet, PDF (78/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
5.6.8.2 Energy Detect Power-Down (EDPD)
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode,
when no energy is present on the line, the PHY is powered down (except the for the management interface, the
SQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy
from 100BASE-TX, 10BASE-T, or Auto-negotiation signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the PHY is powered-down and noth-
ing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and the PHY pow-
ers-up. The PHY automatically resets itself into the state prior to power-down and asserts the INT7 bit of the PHY
Interrupt Source Flag Register register. If the ENERGYON interrupt is enabled, this event will cause a PHY interrupt to
the Interrupt Controller and the power management event detection logic. The first and possibly the second packet to
activate ENERGYON may be lost.
When THE EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is disabled.
When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs
in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP / Crossover Time Configuration Register. When enabled,
the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD NLP / Crossover
Time Configuration Register. When in EDPD mode, the device can also be configured to wake on the reception of one
or two NLPs. Setting the EDPD RX Single NLP Wake Enable bit of the EDPD NLP / Crossover Time Configuration Reg-
ister will enable the device to wake on reception of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared,
the maximum interval for detecting reception of two NLPs to wake from EDPD is configurable via the EDPD RX NLP
Max Interval Detect Select field of the EDPD NLP / Crossover Time Configuration Register.
5.6.9 PHY RESETS
In addition to a chip-level reset, the PHY supports two software-initiated resets. These are discussed in the following
sections.
5.6.9.1 PHY Soft Reset via PMT_CTL Register PHY Reset (PHY_RST) Bit
The PHY soft reset is initiated by writing a ‘1’ to the PHY Reset (PHY_RST) bit of the Power Management Control Reg-
ister (PMT_CTL). This self-clearing bit will return to ‘0’ after approximately 2ms, at which time the PHY reset is complete.
5.6.9.2 PHY Soft Reset via PHY Basic Control Register Bit 15 (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-clearing
bit will return to ‘0’ after approximately 256μs, at which time the PHY reset is complete. The BCR reset initializes the
logic within the PHY, with the exception of register bits marked as NASR (Not Affected by Software Reset).
5.6.10 REQUIRED ETHERNET MAGNETICS
The magnetics selected for use with the device should be an Auto-MDIX style magnetic available from several vendors.
The user is urged to review Application Note 8.13 “Suggested Magnetics” for the latest qualified and suggested mag-
netics. Vendors and part numbers are provided in this application note.
5.6.11 PHY REGISTERS
Please refer to Section 7.5, "PHY Registers," on page 174 for a complete description of the PHY registers.
5.7 EEPROM Controller (EPC)
The device may use an external EEPROM to store the default values for the USB descriptors and the MAC address.
The EEPROM controller supports most “93C46” type EEPROMs. The EEP_SIZE strap selects the size of the EEPROM
attached to the device. When this strap is set to “0”, a 128 byte EEPROM is attached and a total of seven address bits
are used. When this strap is set to “1” a 256/512 byte EEPROM is attached and a total of nine address bits are used.
Note: A 3-wire style 1K/2K/4K EEPROM that is organized for 128 x 8-bit or 256/512 x 8-bit operation must be
used.
DS00001875A-page 78
 2010 - 2015 Microchip Technology Inc.