LAN9500 Datasheet, PDF (46/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 5-40: RX STATUS WORD FORMAT (CONTINUED)
Bits
Description
1
CRC Error
When set, this bit indicates that a CRC error was detected. This bit is also set when the RX_ER pin
is asserted during the reception of a frame even though the CRC may be correct. This bit is not valid
if the received frame is a Runt frame, or a late collision was detected or when the Watchdog Time-
out occurs.
0
RESERVED
5.4.1.3 Flushing the RX FIFO
The device allows for the Host to the flush the entire contents of the FCT RX FIFO. When a flush is activated, the read
and write pointers of the RX FIFO are returned to their reset state.
Before flushing the RX FIFO, the device’s receiver must be stopped, as specified in Section 5.4.1.4. Once the receiver
stop completion is confirmed, the Receive FIFO Flush bit can be set in the Receive Configuration Register (RX_CFG)
on page 120 to initiate the flush operation. This bit is cleared after the flush is complete.
5.4.1.4 Stopping and Starting the Receiver
To stop the receiver, the Host must clear the Receiver Enable (RXEN) bit in the MAC Control Register (MAC_CR) on
page 159. When the receiver is halted, the RXSTOP_INT will be pulsed. Once stopped, the Host can optionally clear
the RX Status and RX FIFOs. The Host must re-enable the receiver by setting the RXEN bit.
5.4.2 TX PATH (USB -> ETHERNET)
The 8 KB TX FIFO buffers USB Bulk Out packets received by the URX. The FCT is responsible for extracting the Ether-
net frames embedded in the USB Bulk Out Packets and passing them to the TLI. The Ethernet frames were segmented
across the USB packets by the Host drivers.
The FCT manages the writing of data into the TX FIFO through the use of two pointers - the tx_wr_ptr and the tx_wr_h-
d_ptr. These pointers are used to manage the storing of USB Bulk Out packets. They support rewinding the stored USB
packet, in the event that the Bulk Out Packet is errored and needs to be retransmitted by the Host. The write side of the
FCT does not perform any processing on the USB packet data. The read side of the TX FIFO is responsible for extract-
ing the Ethernet frames. The Ethernet frames may be split across multiple buffers, as shown in Figure 5-5.
DS00001875A-page 46
 2010 - 2015 Microchip Technology Inc.