LAN9500 Datasheet, PDF (43/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 5-38: FORMAT OF GET STATISTICS DATA STAGE (RX)
Offset
Field
00h RX Good Frames
04h RX CRC Errors
08h RX Runt Frame Errors
0Ch RX Alignment Errors
10h RX Frame Too Long Error
14h RX Later Collision Error
18h RX Bad Frames
1Ch RX FIFO Dropped Frames
TABLE 5-39: FORMAT OF GET STATISTICS DATA STAGE (TX)
Offset
Field
00h TX Good Frames
04h TX Pause Frames
08h TX Single Collisions
0Ch TX Multiple Collisions
10h TX Excessive Collision Errors
14h TX Late Collision Errors
18h TX Buffer Underrun Errors
1Ch TX Excessive Deferral Errors
20h TX Carrier Errors
24h TX Bad Frames
5.4 FIFO Controller (FCT)
The FIFO controller uses a 28 KB internal SRAM to buffer RX and TX traffic. 20 KB is allocated for received Ethernet-
USB traffic (RX buffer), while 8 KB is allocated for USB-Ethernet traffic (TX buffer).Bulk-Out packets from the USB con-
troller are directly stored into the TX buffer. The FCT is responsible for extracting Ethernet frames from the USB packet
data and passing the frames to the MAC.Ethernet Frames are directly stored into the RX buffer and become the basis
for bulk-in packets. The FCT passes the stored data to the UTX in blocks typically 512 or 64 bytes in size, depending
on the current HS/FS USB operating speed.
5.4.1 RX PATH (ETHERNET -> USB)
The 20 KB RX FIFO buffers Ethernet frames received from the TLI. The UTX extracts these frames from the FCT to
form USB Bulk In packets. The Host drivers will ultimately reassemble the Ethernet frames from the USB packets.
The FCT manages the writing of data into the RX FIFO through the use of two pointers - the rx_wr_ptr and the rx_wr_h-
d_ptr. The rx_wr_ptr is used to write Ethernet frame data into the FIFO. The rx_wr_hd_ptr points to the location prior to
the first DWORD of the frame. It is used to write the RX Status Word received from the TLI, upon completion of a frame
transaction. This status word contains status information associated with the frame and the frame transaction. Figure 5-
4 illustrates how a frame is stored in the FIFO, along with pointer usage.
When the RX TLI signals that it has Data ready, the RX TLI controller starts passing the RX packet data to the FCT. The
FCT updates the RX FIFO pointers as the data is written into the FIFO. The last transfer from the TLI is the RX Status
Word.
The FCT may insert 0 - 3 bytes at the start of the Ethernet frame. The value of the RX Data Offset (RXDOFF) field of
the Hardware Configuration Register (HW_CFG) on page 122 determines the number of bytes inserted.
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