LAN9500 Datasheet, PDF (109/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
The NetDetach feature requires assistance of the driver. The driver will monitor the link status of the Ethernet PHY and
program the device appropriately to detach and re-attach to the USB bus upon link up. The following steps illustrate this
process:
1. User disconnects the Ethernet cable.
2. Driver detects assertion of the PHY_INT bit via the interrupt control endpoint. The driver may also detect PHY
interrupt assertion by polling the Interrupt Status Register (INT_STS).
3. Driver reads the Basic Status Register and finds the Link Status bit is deasserted.
4. At this point, the Driver may place the Ethernet PHY into either the Energy Detect Power-Down mode or the PHY
Link Up Detection mode. Section 5.12.2.3, "Enabling Link Status Change (Energy Detect) Wake Events," on
page 107 and Section 5.12.2.4, "Enabling PHY Link Up Wake Events (LAN9500A/LAN9500Ai ONLY)," on
page 108 provide detailed instructions for programming these modes.
5. Driver sets the NetDetach Enable (SMDET_EN) bit in the Hardware Configuration Register (HW_CFG).
6. The device then detaches from the USB bus and disables the USB PLL. The driver is unloaded at this point and
can no longer communicate with the device.
7. At some point in the future, the Ethernet cable is reconnected, or an appropriately configured GPIO pin is
asserted.
8. The device attaches to the USB bus.
9. The driver is loaded and the device is configured by the driver. The driver examines the NetDetach Status
(SMDET_STS) bit in the Hardware Configuration Register (HW_CFG) to determine if it was reloaded as a result
of coming back from a NetDetach operation or for some other reason.
5.13 Resets
The device has the following chip level reset sources:
• Power-On Reset (POR)
• External Chip Reset (nRESET)
• Lite Reset (LRST)
• Soft Reset (SRST)
• USB Reset
• PHY Software Reset
• nTRST
• VBUS_DET
5.13.1 POWER-ON RESET (POR)
A Power-On reset occurs whenever power is initially applied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset for approximately 22mS.
Note 1: The EEPROM contents are loaded by this reset.
2: After the assertion of the POR, the internal Ethernet PHY is put into general power down mode.
5.13.2 EXTERNAL CHIP RESET (NRESET)
A hardware reset will occur when the nRESET pin is driven low. The READY bit in the PMT_CTRL register can be read
by the Host, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the hardware reset, the
READY bit in PMT_CTRL is set high.
After the “READY” bit is set, the device can be configured via its control registers. The nRESET pin is pulled-high inter-
nally by the device and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period
as defined in Section 8.5.3, "Reset and Configuration Strap Timing," on page 197. If nRESET is unused, the device must
be reset following power-up via a soft reset (SRST).
Note 1: After the assertion of nRESET, the internal Ethernet PHY is put into general power down mode.
2: nRESET is ignored when the device is in the UNPOWERED state. As in the UNPOWERED state the entire
chip is held in reset.
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DS00001875A-page 109