LAN9500 Datasheet, PDF (146/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
7.3.20 GENERAL PURPOSE IO WAKE ENABLE AND POLARITY REGISTER (GPIO_WAKE)
Address:
064h
Size:
32 bits
This register enables the GPIOs to function as wake events for the device when asserted. It also allows the polarity used
for a wake event/interrupt to be configured.
Note: GPIOs must not cause a wake event to the device when not configured as a GPIO.
Bits
Description
31 (LAN9500A/LAN9500Ai ONLY, Otherwise RESERVED)
30:27
26:16
PHY Link Up Enable (PHY_LINKUP_EN)
Setting this bit enables the use of GPIO7 to signal a PHY Link Up event when
in SUSPEND0 or SUSPEND 3 state. In addition to setting this bit, the
parameters for GPIO7 must be set as discussed in Section 5.12.2.4,
"Enabling PHY Link Up Wake Events (LAN9500A/LAN9500Ai ONLY)," on
page 108 in order for signaling to occur.
RESERVED
GPIO Polarity 0-10 (GPIOPOLn)
0 = Wakeup/interrupt is triggered when GPIO is driven low
1 = Wakeup/interrupt is triggered when GPIO is driven high
15:11
10:0
GPIOPOL0 - bit 16
GPIOPOL1 - bit 17
GPIOPOL2 - bit 18
GPIOPOL3 - bit 19
GPIOPOL4 - bit 20
GPIOPOL5 - bit 21
GPIOPOL6 - bit 22
GPIOPOL7 - bit 23
GPIOPOL8 - bit 24
GPIOPOL9 - bit 25
GPIOPOL10 - bit 26
RESERVED
GPIO Wake 0-10 (GPIOWKn)
0 = The GPIO can not wake up the device.
1 = The GPIO can trigger a wake up event.
GPIOWK0 - bit 0
GPIOWK1 - bit 1
GPIOWK2 - bit 2
GPIOWK3 - bit 3
GPIOWK4 - bit 4
GPIOWK5 - bit 5
GPIOWK6 - bit 6
GPIOWK7 - bit 7
GPIOWK8 - bit 8
GPIOWK9 - bit 9
GPIOWK10 - bit 10
Note: (LAN9500A/LAN9500Ai ONLY):
This field is protected by Reset Protection (RST_PROTECT).
Note 7-16 (LAN9500/LAN9500i ONLY): 000h
Type
R/W
RO
R/W
RO
R/W
Default
0b
-
000h
-
Note 7-16
(LAN9500A/LAN9500Ai ONLY):
The default value of this field is loaded from the associated bytes of the EEPROM. The high order
unused bits of the EEPROM are ignored. If no EEPROM is present, the default value of each bit in
the field is 0. A USB Reset or Lite Reset (LRST) will cause this field to be restored to the image
value last loaded from EEPROM, or will cause the value of each bit to be set to 0 if no EEPROM is
present.
DS00001875A-page 146
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