LAN9500 Datasheet, PDF (69/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
5.5.8.1 TX Checksum Calculation
The TX checksum calculation is performed using the same operation as the RX checksum shown in Section 5.5.7.1,
with the exception that the calculation starts as indicated by the preamble, and the transmitted checksum is the one’s-
compliment of the final calculation.
Note:
When the TX checksum offload feature is invoked, if the calculated checksum is 0000h, it is left unaltered.
UDP checksums are optional under IPv4, and a zero checksum calculated by the TX checksum offload
feature will erroneously indicate to the receiver that no checksum was calculated, however, the packet will
typically not be rejected by the receiver. Under IPv6, however, according to RFC 2460, the UDP checksum
is not optional. A calculated checksum that yields a result of zero must be changed to FFFFh for insertion
into the UDP header. IPv6 receivers discard UDP packets containing a zero checksum. Thus, this feature
must not be used for UDP checksum calculation under IPv6.
5.5.9 MAC CONTROL AND STATUS REGISTERS (MCSR)
Please refer to Section 7.4, "MAC Control and Status Registers," on page 158 for a complete description of the MCSR.
5.6 10/100 Internal Ethernet PHY
The device integrates an IEEE 802.3 Physical Layer for Twisted Pair Ethernet applications. The PHY can be configured
for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in either Full or Half Duplex configura-
tions. The PHY block includes auto-negotiation. Minimal external components are required for the utilization of the inter-
nal PHY.
The device provides an option to use an external PHY in place of the internal PHY. The external PHY can be connected
via the Media Independent Interface (MII) port. This option is useful for supporting Home PNA operations. When an
external PHY is used, the internal PHY must be placed into general power down via a PHY reset (refer to Section 5.6.9,
"PHY Resets," on page 78 for further information).
Functionally, the internal PHY can be divided into the following sections:
• 100Base-TX transmit and receive
• 10Base-T transmit and receive
• Internal MII interface to the Ethernet Media Access Controller
• Auto-negotiation to automatically determine the best speed and duplex possible
• Management Control to read status registers and write control registers
5.6.1 100BASE-TX TRANSMIT
The data path of the 100Base-TX is shown in Figure 5-17. Each major block is explained in the following sections.
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DS00001875A-page 69