LAN9500 Datasheet, PDF (116/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
7.0 REGISTER DESCRIPTIONS
7.1 Register Nomenclature
Table 7-1 describes the register bit attributes used throughout this document.
TABLE 7-1: REGISTER BIT TYPES
Register Bit
Type Notation
Register Bit Description
R
Read: A register or bit with this attribute can be read.
W
Write: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
RS
Read to Set: This bit is set on read.
WO
WC
WAC
RC
LL
LH
SC
RO/LH
NASR
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Clear: writing a one clears the value. Writing a zero has no effect.
Write Anything to Clear: writing anything clears the value.
Read to Clear: Contents is cleared after the read. Writes have no effect.
Latch Low: Clear on read of register.
Latch High: Clear on read of register.
Self-Clearing: Contents is self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
Read Only, Latch High: This mode is used by the Ethernet PHY registers. Bits with
this attribute will stay high until the bit is read. After it a read, the bit will remain high,
but will change to low if the condition that caused the bit to go high is removed. If the
bit has not been read the bit will remain high regardless of if its cause has been
removed.
Not Affected by Software Reset. The state of NASR bits does not change on
assertion of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros, unless otherwise
indicated, to ensure future compatibility. The value of reserved bits is not guaranteed
on a read.
7.2 Register Memory Map
TABLE 7-2: LAN950X REGISTER MEMORY MAP
Address
Symbol
000h - 0FFh
100h - 1FCh
SCSR
MCSR
Register Name
System Control and Status Registers
MAC Control and Status Registers
DS00001875A-page 116
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