LAN9500 Datasheet, PDF (127/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

7.3.8 POWER MANAGEMENT CONTROL REGISTER (PMT_CTL)
Address:
020h
Size:
32 bits
LAN950x
This register controls the power management features.
Bits
31:10
9
8
7
Description
RESERVED
Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS)
When set, the Remote Wakeup Frame Received (WUFR) and Magic Packet
Received (MPFR) status signals in the MAC WUCSR will clear upon the
completion of a resume sequence.
When set, this bit also affects the WUPS field. WUPS[1] will clear upon
completion of a resume event.
Only resume sequences initiated by a wakeup frame or magic packet are
affected by RES_CLR_WKP_STS.
When cleared, the wakeup status signals are not cleared after a resume.
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN)
when asserted, all wakeup enable bits are cleared after a resume sequence,
initiated from a remote wakeup, completes. Resumes initiated by the host do
not clear the wakeup enables.
Device Ready (READY)
When set, this bit indicates that the device is in the NORMAL state and the
initial hardware configuration of the device has completed.
Note 1: This bit is useful for events (USB Reset) that do not trigger a soft
disconnect.
2: In the case where no PHY clocks are present to complete a system
reset this bit will not be set until the watchdog timer expires. This is
applicable for a Lite Reset and when transitioning to the Normal
Configured state.
6:5 Suspend Mode (SUSPEND_MODE)
Indicates which suspend power state to use after the Host suspends the
device.
If the device is deconfigured, it transitions to the NORMAL Unconfigured
state and this register will reset to the value 10b.
SUSPEND_MODE encoding:
00 = SUSPEND0
01 = SUSPEND1
10 = SUSPEND2
11 = Note 7-9
Note: It is not valid to select any suspend variant besides SUSPEND2
when in the NORMAL Unconfigured state.
4 PHY Reset (PHY_RST)
Writing a '1' to this bit resets the PHY. The internal logic automatically holds
the PHY reset for a minimum of 2 ms. When the PHY is released from reset,
this bit is automatically cleared. All writes to this bit are ignored while this bit
is high.
Note: The device will NAK all USB transfers until the PHY reset
completes.
3 Wake-On-Lan Enable (WOL_EN)
Enables WOL as a wakeup event.
Type
RO
R/W
R/W
RO
R/W
SC
R/W
Default
-
0b
1b
0b
10b
0b
0b
 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 127