LAN9500 Datasheet, PDF (13/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 3-1:
Num Pins
MII INTERFACE PINS (CONTINUED)
Name
Symbol
Buffer
Type
MII Collision
Detect
(Internal PHY
Mode)
COL
IS/O8
(PU)
MII Collision
COL
Detect
(External PHY
Mode)
1
General GPIO0
Purpose I/O 0
(Internal PHY
Mode Only)
IS
(PD)
IS/O8/
OD8
(PU)
Management
Data
(Internal PHY
Mode)
MDIO
Management
Data
(External PHY
Mode)
MDIO
1
General GPIO1
Purpose I/O 1
(Internal PHY
Mode Only)
IS/O8
(PU)
IS/O8
(PD)
IS/O8/
OD8
(PU)
Management
Clock
(Internal PHY
Mode)
MDC
Management
1
Clock
(External PHY
Mode)
MDC
General
Purpose I/O 2
(Internal PHY
Mode Only)
GPIO2
IS/O8
(PU)
O8
(PD)
IS/O8/
OD8
(PU)
Description
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates a
collision event.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Note:
(LAN9500A/LAN9500Ai ONLY):
This pin may be used to signal PME
when Internal PHY and PME modes of
operation are in effect. Refer to Section
6.0, "PME Operation," on page 112 for
additional information.
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, this pin provides the
management data to/from the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Note:
(LAN9500A/LAN9500Ai ONLY):
This pin may serve as the
PME_MODE_SEL input when Internal
PHY and PME modes of operation are in
effect. Refer to Section 6.0, "PME
Operation," on page 112 for additional
information.
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, this pin outputs the
management clock to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
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DS00001875A-page 13