LAN9500 Datasheet, PDF (56/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
• Medium allocation (collision detection, except in full-duplex operation)
• Contention resolution (collision handling, except in full-duplex operation)
• Flow control during full-duplex mode
• Decoding of control frames (PAUSE command) and disabling the transmitter
• Generation of control frames
• Interface to the internal PHY and optional external PHY.
• Checksum offload engine for calculation of layer 3 transmit and receive checksum.
The transmit and receive data paths are separate within the device from the MAC to Host interface, allowing the highest
performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these
busses.
A third internal bus is used to access the MAC’s “Control and Status Registers” (CSR’s). This bus is also accessible
from the Host.
On the backend, the MAC interfaces with the 10/100 PHY through an MII (Media Independent Interface) port which is
internal to the device. In addition, there is an external MII interface supporting optional PHY devices. The MAC CSR's
also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Inter-
face) bus.
The receive and transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the Host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks reducing and
minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths.
5.5.1 FLOW CONTROL
The device’s Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also sup-
ports half-duplex flow control using back pressure. In order for flow control to be invoked, the Flow Control Enable
(FCEN) bit of the Flow Control Register (FLOW) must be set.
5.5.1.1 Full-Duplex Flow Control
The pause operation inhibits data transmission of data frames for a specified period of time. A Pause operation consists
of a frame containing the globally assigned multicast address (01-80-C2-00-00-01), the PAUSE opcode, and a param-
eter indicating the quantum of slot time (512 bit times) to inhibit data transmissions. The PAUSE parameter may range
from 0 to 65,535 slot times. The Ethernet MAC logic, on receiving a frame with the reserved multicast address and
PAUSE opcode, inhibits data frame transmissions for the length of time indicated. If a Pause request is received while
a transmission is in progress, then the pause will take effect after the transmission is complete. Control frames are
received and processed by the MAC and are passed on.
The device will automatically transmit pause frames based on the settings of Automatic Flow Control Configuration Reg-
ister (AFC_CFG) and the Flow Control Register (FLOW). When the RX FIFO reaches the level set in the Automatic Flow
Control High Level (AFC_HI) field of AFC_CFG, the device will transmit a pause frame. The pause time field that is trans-
mitted is set in the Pause Time (FCPT) field of the FLOW register. When the RX FIFO drops below the level set in the
Automatic Flow Control Low Level (AFC_LO) field of AFC_CFG, the device will automatically transmit a pause frame
with a pause time of zero. The device will only send another pause frame when the RX FIFO level falls below AFC_LO
and then exceeds AFC_HI again.
5.5.1.2 Half-Duplex Flow Control (Backpressure)
In half-duplex mode, back pressure is used for flow control. Whenever the RX FIFO crosses a certain threshold level,
the MAC starts sending a Jam signal. The MAC transmit logic enters a state at the end of current transmission (if any),
where it waits for the beginning of a received frame. Once a new frame starts, the MAC starts sending the jam signal,
which will result in a collision. After sensing the collision, the remote station will back off its transmission. The MAC con-
tinues sending the jam signal to make other stations defer transmission. The MAC only generates this collision-based
back pressure when it receives a new frame, in order to avoid any late collisions.
The device will automatically assert back pressure based on the setting of the Automatic Flow Control Configuration
Register (AFC_CFG). When the RX FIFO reaches the level set by Automatic Flow Control High Level (AFC_HI) field of
AFC_CFG, the Back pressure Duration Timer will start. The device will assert back pressure for any received frames,
as defined by the values of the FCANY, FCADD, FCMULT and FCBRD control bits of AFC_CFG. This continues until
the Back pressure Duration Timer reaches the time specified by the BACK_DUR field of AFC_CFG. After the
BACK_DUR time period has elapsed, the receiver will accept one frame. If, after receiving one RX frame, the RX FIFO
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