LAN9500 Datasheet, PDF (15/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 3-1: MII INTERFACE PINS (CONTINUED)
Num Pins
Name
Symbol
Transmit Data
1
(Internal PHY
Mode)
TXD1
Transmit Data
1
(External PHY
Mode)
TXD1
General
GPIO5
1
Purpose I/O 5
(Internal PHY
Mode Only)
Remote
Wakeup
Configuration
Strap
RMT_WKP
Buffer
Type
IS/O8
(PD)
O8
(PD)
Description
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, this pin functions as the
transmit data 1 output to the external PHY.
IS/O8/
OD8
(PU)
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
IS
(PD)
This strap configures the default descriptor values
to support remote wakeup. This strap is overridden
by the EEPROM.
0 = Remote wakeup is not supported.
1 = Remote wakeup is supported.
See Note 3-1 for more information on configuration
straps.
Transmit Data
0
(Internal PHY
Mode)
TXD0
IS/O8
(PD)
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
Transmit Data
0
(External PHY
Mode)
TXD0
O8
(PD)
In external PHY mode, this pin functions as the
transmit data 0 output to the external PHY.
General
GPIO4
1
Purpose I/O 4
(Internal PHY
Mode Only)
IS/O8/
OD8
(PU)
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
EEPROM
Disable
Configuration
Strap
EEP_DISABLE
IS
(PD)
This strap disables the autoloading of the
EEPROM contents. The assertion of this strap
does not prevent register access to the EEPROM.
0 = EEPROM is recognized if present.
1 = EEPROM is not recognized even if it is
present.
1
Note 3-1
See Note 3-1 for more information on configuration
straps.
Transmit Clock
(Internal PHY
Mode)
TXCLK
IS/O8
(PU)
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
Transmit Clock
(External PHY
Mode)
TXCLK
IS
(PU)
In external PHY mode, this pin is the transmitter
clock input from the external PHY.
Configuration strap values are latched on Power-On Reset (POR) or External Chip Reset (nRESET).
Configuration straps are identified by an underlined symbol name. Pins that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to Section 5.14,
"Configuration Straps," on page 110 for additional information.
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DS00001875A-page 15