LAN9500 Datasheet, PDF (55/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
5.4.2.10 Flushing the TX FIFO
The device allows for the Host to the flush the entire contents of the FCT TX FIFO. When a flush is activated, the read
and write pointers for the TX FIFO are returned to their reset state.
Before flushing the TX FIFO, the device’s transmitter must be stopped, as specified in Section 5.4.2.11. Once the trans-
mitter stop completion is confirmed, the Transmit FIFO Flush bit can be set in the Transmit Configuration Register
(TX_CFG) on page 121. This bit is cleared after the flush is complete.
5.4.2.11 Stopping and Starting the Transmitter
To halt the transmitter, the Host must set the Stop Transmitter (STOP_TX) bit in the TX_CFG register. The transmitter
will finish sending the current frame (if there is a frame transmission in progress). When the transmitter has received
the TX Status for the current frame, it will clear the STOP_TX and TX_ON bits in the TX_CFG register, and will pulse
TXSTOP_INT.
Once stopped, the Host can optionally flush the TX FIFO, and can optionally disable the MAC by clearing TXEN. The
Host must re-enable the transmitter by setting the TX_ON and TXEN bits. If the there are frames pending in the TX FIFO
(i.e., the TX FIFO was not purged), the transmission will resume with this data.
Note: The TX Stop mechanism described here assumes that the MAC will return a status for every TX frame.
5.4.3 ARBITRATION
The FCT must arbitrate access to the RX and TX FIFOs to the URX, UTX, TLI RX, and TLI TX. Highest priority is always
given to the USB. The TLI RX/TX can be wait stated as frames buffering exists in the TLI (2 KB TX, 128 Byte RX).
FCT strict priority order:
1. URX Request (Bulk Out Packet)
2. UTX Request (Bulk In Packet)
3. TLI RX (Received Ethernet Frame)
4. TLI TX (Transmitted Ethernet Frame)
Note: By nature of the USB bus and UDC operation, the URX and UTX should not request bandwidth simultane-
ously.
5.5 10/100 Ethernet MAC
The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ether-
net/IEEE 802.3-compliant node and provides an interface between the Host subsystem and the internal Ethernet PHY.
The MAC can operate in either 100-Mbps or 10-Mbps mode.
The MAC operates in both half-duplex and full-duplex modes. When operating in half-duplex mode, the MAC complies
fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard) and ANSI/IEEE 802.3 standards. When operating in full-
duplex mode, the MAC complies with IEEE 802.3x full-duplex operation standard.
The MAC provides programmable enhanced features designed to minimize Host supervision, bus utilization, and pre-
or post-message processing. These features include the ability to disable retries after a collision, dynamic FCS (Frame
Check Sequence) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum
frame size attributes, layer 3 checksum calculation for transmit and receive operations, and automatic retransmission
and detection of collision frames.
The MAC can sustain transmission or reception of minimally-sized back-to-back packets at full line speed with an inter-
packet gap (IPG) of 9.6 microseconds for 10 Mbps and 0.96 microseconds for 100 Mbps.
The primary attributes of the MAC Function are:
• Transmit and receive message data encapsulation
• Framing (frame boundary delimitation, frame synchronization)
• Error detection (physical medium transmission errors)
• Media access management
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DS00001875A-page 55