LAN9500 Datasheet, PDF (110/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
5.13.3 LITE RESET (LRST)
This reset is initiated via the LRST bit in the Section 7.3.5, "Hardware Configuration Register (HW_CFG)". It will reset
the entire chip with the exception of the USB Device Controller and the USB PHY (UDC, parts of the CTL, and the USB
PHY). The PLL is not turned off.
Note 1: This reset does not cause the USB contents from the EEPROM to be reloaded.
2: This reset does not place the device into the Unconfigured state.
3: After the LRST, the USB pipes corresponding to the Bulk In, Bulk Out, and Interrupt endpoints must be reset.
This process entails clearing the device’s ENDPOINT_HALT feature and resetting the data toggle on the
host side.
5.13.4 SOFT RESET (SRST)
A Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will return to ‘0’ after
approximately 2 μs, at which time the Soft Reset is complete. Soft reset does not clear control register bits marked as
NASR.
Note 1: The EEPROM contents are reloaded by this reset.
2: After the assertion of the SRST the internal Ethernet PHY is put into general power down mode.
Writing SRST=1 will cause the device to disconnect from the USB shortly after the first good OUT Data pkt during the
Data Phase. In HS mode, a brief delay will allow enough time for the device to send the ACK for the Data Stage, but the
device will be disconnected (causing a 3-strikes timeout failure) for any next transaction (e.g., the Status Stage, or a
repeated Data Stage, if there were any bus errors). In FS mode, the brief delay will be short enough that the device will
disconnect during the ACK pkt, causing CRC, bit-stuff, etc. errors on USB. To the USB Host, the aforementioned behav-
iors are the same as what happens during any Surprise Removal of a USB Device. This behavior is completely normal,
and a compliant Host must be tolerant of it.
5.13.5 USB RESET
A USB reset causes a reset of the entire chip with the exception of the USB Device Controller and the USB PHY (UDC,
parts of the CTL, and the USB PHY). The PLL is not turned off. It will occur after a POR, nRESET, or SRST (These will
all force disconnects of the USB bus). After a USB reset, the READY bit in the PMT_CTRL register can be read by the
Host and will read back a ‘0’ until the EEPROM contents are loaded (provided one is present). Upon completion of the
EEPROM contents load, the READY bit in PMT_CTRL is set high, and the device can be configured via its control reg-
isters.
Note 1: This reset does not cause the USB contents from the EEPROM to be reloaded. Only the MAC address is
reloaded.
2: After the assertion of the USB Reset the internal Ethernet PHY is put into general power down mode.
5.13.6 PHY SOFTWARE RESET
The Ethernet PHY can be reset via two software-initiated resets. Please refer to Section 5.6.9, "PHY Resets," on
page 78 for details.
5.13.7 NTRST
This active-low reset is used by the TAP controller.
5.13.8 VBUS_DET
The removal of USB power causes the device to transition to the UNPOWERED state. The chip is held in reset while in
the UNPOWERED state.
Note 1: After VBUS_DET is asserted, the contents of the EEPROM are reloaded.
2: After transitioning out of the UNPOWERED state, the internal Ethernet PHY is in general power down mode.
DS00001875A-page 110
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