LAN9500 Datasheet, PDF (166/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
7.4.6 MII ACCESS REGISTER (MII_ACCESS)
Address:
114h
Size:
32 bits
This register is used to control the management cycles to the internal PHY.
Bits
31:16 RESERVED
Description
15:11
10:6
5:2
PHY Address
For every access to this register, this field must be set to 00001b.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY.
RESERVED
1 MII Write (MIIWnR)
Setting this bit tells the PHY that this will be a write operation using the MII
data register. If this bit is not set, this will be a read operation, packing the
data in the MII data register.
0 MII Busy (MIIBZY)
This bit must be polled to determine when the MII register access is
complete. This bit must read a logical 0 before writing to this register or to
the MII data register. The LAN driver software must set (1) this bit in order
for the Host to read or write any of the MII PHY registers.
During a MII register access, this bit will be set, signifying a read or write
access is in progress. The MII data register must be kept valid until the MAC
clears this bit during a PHY write operation. The MII data register is invalid
until the MAC has cleared this bit during a PHY read operation.
Type
RO
R/W
R/W
RO
R/W
SC
Default
-
00000b
00000b
-
0b
0b
DS00001875A-page 166
 2010 - 2015 Microchip Technology Inc.