LAN9500 Datasheet, PDF (25/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
5.0 FUNCTIONAL DESCRIPTION
5.1 Functional Overview
The LAN950x USB 2.0 to 10/100 Ethernet Controller consists of the following major functional blocks:
• USB PHY
• USB 2.0 Device Controller (UDC)
• FIFO Controller (FCT) and Associated SRAM
• 10/100 Ethernet MAC
• 10/100 Internal Ethernet PHY
• IEEE 1149.1 Tap Controller
• EEPROM Controller (EPC)
The following sections discuss the features of each block. A block diagram of the device is shown in FIGURE 2-1:
LAN950x Block Diagram on page 7.
5.2 USB PHY
The USB PHY has the USB interface on one end, and connects to the USB 2.0 Device Controller on the other. The
Parallel-to-serial/serial-to-parallel conversion, bit stuffing, and NRZI coding / decoding are handled in the PHY block.
The PHY is capable of operating in the USB 1.1 and 2.0 modes.
5.3 USB 2.0 Device Controller (UDC)
The USB functionality in the device consists of five major parts. The USB PHY (discussed in Section 5.2), UCB (USB
Common Block), UDC (USB Device Controller), URX (USB Bulk Out Receiver), UTX (USB Bulk In Receiver), and CTL
(USB Control Block). They are represented as the USB PHY and UDC, collectively, in FIGURE 2-1: LAN950x Block
Diagram on page 7.
The UCB generates various clocks, including the system clocks of the device. The URX and UTX implement the Bulk
Out and Bulk In endpoints respectively. The CTL manages control and interrupt endpoints.
The UDC is a USB low-level protocol interpreter. The UDC controls the USB bus protocol, packet generation/extraction,
PID/Device ID parsing, and CRC coding/decoding with autonomous error handling. It is capable of operating either in
USB 1.1 or 2.0 compliant modes. It has autonomous protocol handling functions like stall condition clearing on setup
packets, suspend/resume/reset conditions, and remote wakeup. It also autonomously handles error conditions such as
retry for CRC errors, Data toggle errors, and generation of NYET, STALL, ACK and NACK, depending on the endpoint
buffer status.
The UDC is configured to support one configuration, one interface, one alternate setting, and four endpoints.
5.3.1 SUPPORTED ENDPOINTS
Table 5-1lists the supported endpoints. The following subsections discuss these endpoints in detail.
TABLE 5-1: SUPPORTED ENDPOINTS
Endpoint
Number
0
1
2
3
Description
Control Endpoint
Bulk In Endpoint
Bulk Out Endpoint
Interrupt Endpoint
The URX and UTX implement the Bulk Out and Bulk In endpoints, respectively. The CTL manages the Control and Inter-
rupt endpoints.
 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 25