LAN9500 Datasheet, PDF (124/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
Bits
Description
1 Burst Cap Enable (BCE)
This register enables use of the burst cap register, Section 7.3.14, "Burst Cap
Register (BURST_CAP)".
Type
R/W
Default
0b
0 = Burst Cap register is not used to limit the TX burst size.
1 = Burst Cap register is used to limit the TX burst size.
0 Soft Reset (SRST)
SC
0b
Writing 1 generates a software initiated reset of the device. If an external
Ethernet PHY is used, it will be reset as well.
A software reset will result in the contents of the EEPROM being reloaded.
While the reset sequence is in progress, the USB PHY will be disconnected.
After the device has been reinitialized, it will take the PHY out of the
disconnect state and be visible to the Host.
Note 7-6
The default value of this bit depends on whether a NetDetach event occurred. If set, the event
occurred.
Note 7-7
The default value of this field is determined by the value of the PHY Boost field of the Configuration
Flags contained within the EEPROM, if present. If no EEPROM is present, 00b is the default. A USB
Reset or Lite Reset (LRST) will cause this field to be restored to the image value last loaded from
EEPROM, or to be set to 00b if no EEPROM is present.
Note 7-8 The PHY_SEL pin determines the default value.
DS00001875A-page 124
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