LAN9500 Datasheet, PDF (123/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
Bits
Description
10:9 RX Data Offset (RXDOFF)
This field controls the amount of offset, in bytes, that is added to the
beginning of an RX Data packet. The start of the valid data will be shifted by
the amount of bytes specified in this field. An offset of 0-3 bytes is a valid
number of offset bytes.
Type
R/W
Note: This register may not be modified after the RX datapath has been
enabled.
8 Stall Bulk Out Pipe Disable (SBP)
R/W
This bit controls the operation of the Bulk Out pipe when the FCT detects the
loss of sync condition. Please refer to Section 5.4.2.5, "TX Error Detection"
for details.
0 = Stall the Bulk Out pipe when loss of sync detected.
1 = Do not stall the Bulk Out pipe when loss of sync detected.
7 Internal MII Visibility Enable (IME)
RW
This register enables a subset of the MII interface to be visible on unused
pins when configured for the internal Ethernet PHY mode. The pins controlled
by the IME bit are comprised of the pins listed in Table 3-1, “MII Interface
Pins,” on page 12 and the nPHY_INT pin.
0 = The MII signals are not visible. The MII pins function as inputs.
1 = The MII signals are visible. The MII pins function as outputs.
Note 1: This register has no affect when using an external PHY.
2: The IME has priority over the GPIO_CFG register. When IME is
asserted, the pins CRS, MDC, MDIO, COL, TXD3, TXD2, TXD1,
and TXD0 can not be configured for GPIO operation.
6 Discard Errored Received Ethernet Frame (DRP)
R/W
This bit will cause errored Ethernet frames to be discarded when enabled.
0 = Do not discard errored Ethernet frames
1 = Discard errored Ethernet frames.
5 Multiple Ethernet Frames per USB Packet (MEF)
R/W
This bit enables the USB transmit direction to pack multiple Ethernet frames
per USB packet whenever possible.
0 = Support no more than one Ethernet frame per USB packet
1 = Support packing multiple Ethernet frames per USB packet
Note: The URX supports this mode by default.
4 EEPROM Time-out Control (ETC)
R/W
This bit controls the length of time used by the EEPOM controller to detect
a time-out.
0 = Time-out occurs if no response received from EEPROM after 30 ms.
1 = Time-out occurs if no response received from EEPROM after 1.28 us.
3 Soft Lite Reset (LRST)
SC
Writing 1 generates the lite software reset of the device.
A lite reset will not affect the UDC. Additionally, the contents of the EEPROM
will not be reloaded. This reset will not cause the USB PHY to be
disconnected. This bit clears after the reset sequence has completed.
2 PHY Select (PSEL)
RO
This bit indicates whether an internal or external Ethernet PHY is being used.
0 = Internal Ethernet PHY is used.
1 = External Ethernet PHY is used.
Default
00b
0b
0b
0b
0b
0b
0b
Note 7-8
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DS00001875A-page 123