LAN9500 Datasheet, PDF (14/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 3-1:
Num Pins
MII INTERFACE PINS (CONTINUED)
Name
Symbol
Buffer
Type
Transmit Data
3
(Internal PHY
Mode)
TXD3
IS/O8
(PU)
Transmit Data
3
(External PHY
Mode)
General
Purpose I/O 7
(Internal PHY
Mode Only)
TXD3
GPIO7
O8
(PU)
IS/O8/
OD8
(PU)
1
EEPROM Size EEP_SIZE
Configuration
Strap
IS
(PU)
Description
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, this pin functions as the
transmit data 3 output to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Note:
(LAN9500A/LAN9500Ai ONLY):
GPIO7 may provide additional PHY Link
Up related functionality. Refer to Section
5.12.2.4, "Enabling PHY Link Up Wake
Events (LAN9500A/LAN9500Ai ONLY),"
on page 108 for additional information.
The EEP_SIZE strap selects the size of the
EEPROM attached to the device.
0 = 128 byte EEPROM is attached and a total of
seven address bits are used.
1 = 256/512 byte EEPROM is attached and a total
of nine address bits are used.
Note:
A 3-wire style 1K/2K/4K EEPROM that is
organized for 128 x 8-bit or 256/512 x 8-
bit operation must be used.
See Note 3-1 for more information on configuration
straps.
Transmit Data
2
(Internal PHY
Mode)
TXD2
IS/O8
(PD)
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
Transmit Data
2
(External PHY
Mode)
TXD2
O8
(PD)
In external PHY mode, this pin functions as the
transmit data 2 output to the external PHY.
General
GPIO6
1
Purpose I/O 6
(Internal PHY
Mode Only)
IS/O8/
OD8
(PU)
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
USB Port
Swap
Configuration
Strap
PORT_SWAP
IS
(PD)
Swaps the mapping of USBDP and USBDM.
0 = USBDP maps to the USB D+ line and USBDM
maps to the USB D- line.
1 = USBDP maps to the USB D- line. USBDM
maps to the USB D+ line.
See Note 3-1 for more information on configuration
straps.
DS00001875A-page 14
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