LAN9500 Datasheet, PDF (103/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
5.12.1.2 LAN9500A/LAN9500Ai Wake Detection Logic
A simplified diagram of the wake event detection logic for LAN9500A/LAN9500Ai is shown in Figure 5-33.
FIGURE 5-33:
WAKE EVENT DETECTION BLOCK DIAGRAM (LAN9500A/LAN9500AI)
WUEN
(WUSCR Register)
RW
WUFR
(WUSCR Register)
MPEN
(WUSCR Register)
RW
MPR
(WUSCR Register)
GUEN
(WUSCR Register)
RW
WUEN
(WUSCR Register)
RW
WUFR
(WUSCR Register)
PFDA_EN
(WUSCR Register)
RW
PFDA_FR
(WUSCR Register)
BCAST_EN
(WUSCR Register)
RW
BCAST_FR
(WUCSR Register)
Good Frame
Received
SUSPEND0
SUSPEND1
SUSPEND2
SUSPEND3
GPIO0_DET
.
.
.
GPIO10_DET
WOL_EN
(PMT_CTL Register)
RW
WUPS[1]
(PMT_CTL Register)
ED_EN
(PMT_CTL Register)
RW
WUPS[0]
(PMT_CTL Register)
remote_wake
Note: Diagram does not represent actual hardware implementation.
The functionality of GPIOs 0-6 and GPIOs 8-10 is slightly different. The functionality of GPIO7 is similar to that of GPIOs
0-6, with the additional requirement that it must cause a wakeup event when enabled for use in PHY Link Up detection.
Note: GPIOs 0-7 are only available for use during internal PHY Mode of operation. The functionality of GPIOs 0-
6 is depicted in Figure 5-34, while that of GPIO7 is shown in Figure 5-35.
GPIOs 8-10 are available for use in both internal and external PHY mode of operation. Their functionality is depicted in
Figure 5-36.
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DS00001875A-page 103