LAN9500 Datasheet, PDF (163/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

7.4.3 MAC ADDRESS LOW REGISTER (ADDRL)
Address:
108h
Size:
LAN950x
32 bits
This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the first octet of the
Ethernet frame.
Note: (LAN9500A/LAN9500Ai ONLY):
This register is protected by Reset Protection (RST_PROTECT).
Bits
Description
31:0 Physical Address [31:0]
This field contains the lower 32 bits (32:0) of the Physical Address of this
MAC device.
Type
R/W
Default
FFFF_FFFFh
Table 7-5 illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet
physical address.
TABLE 7-5: ADDRL, ADDRH BYTE ORDERING
ADDRL, ADDRH
ADDRL[7:0]
ADDRL[15:8]
ADDRL[23:16]
ADDRL[31:24]
ADDRH[7:0]
ADDRH[15:8]
Order of Reception on Ethernet
1^st
2^nd
3^rd
4^th
5^th
6^th
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would
be programmed as shown in Figure 7-1.
FIGURE 7-1:
EXAMPLE ADDRL, ADDRH ADDRESS ORDERING
31 24 23 16 15 8 7 0
xx
xx
0xBC 0x9A
ADDRH
31 24 23 16 15 8 7
0
0x78 0x56 0x34 0x12
ADDRL
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DS00001875A-page 163