LAN9500 Datasheet, PDF (50/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
• Buffer Size is Zero Error - The buffer length field is zero.
• Buffer Size Error - The total sum of the buffers received is not equal to the frame length.
Note 1: The FCT can be configured to stall the Bulk Out pipe when a Transmit Error is detected. This is accom-
plished via the Stall Bulk Out Pipe Disable (SBP) bit of the Hardware Configuration Register (HW_CFG).
Please refer to Section 7.3.5, "Hardware Configuration Register (HW_CFG)," on page 122 for further
details.
2: A TX Error is a catastrophic condition. The device should be reset in order to recover from it.
5.4.2.6 TX Status Format
After an Ethernet frame is transmitted, the TLI returns the TX Status Word to the FCT, as illustrated in Table 5-44. The
contents of the TX Status Word is used for statistics generation and interrupt status creation. Please refer to Section
5.3.1.7, "Statistics," on page 36 and Section 7.3.2, "Interrupt Status Register (INT_STS)" for further details.
TABLE 5-44: TX STATUS WORD FORMAT
Bits
Description
31:16
15
14:12
11
10
9
8
7
6:3
2
1
0
RESERVED
Error Status (ES)
When set, this bit indicates that the TLI has reported an error. This bit is the logical OR of bits 11, 10,
9, 8, 2, 1 in this status word.
RESERVED
Loss of Carrier
When set, this bit indicates the loss of carrier during transmission.
No Carrier
When set, this bit indicates that the carrier signal from the transceiver was not present during
transmission.
Late Collision
When set, indicates that the packet transmission was aborted after the collision window of 64 bytes.
Excessive Collisions
When set, this bit indicates that the transmission was aborted after 16 collisions while attempting to
transmit the current packet.
RESERVED
Collision Count
This counter indicates the number of collisions that occurred before the packet was transmitted. It is
not valid when excessive collisions (bit 8) is also set.
Excessive Deferral
If the deferred bit is set in the control register, the setting of the excessive deferral bit indicates that
the transmission has ended because of a deferral of over 24288 bit times during transmission.
Underrun Error
When set, this bit indicates that the transmitter aborted the associated frame because of an underrun
condition on the TX Data FIFO. TX Underrun will cause the assertion of the TDFU flag in the Interrupt
Status Register (INT_STS) and the interrupt endpoint.
Deferred
When set, this bit indicates that the current packet transmission was deferred.
DS00001875A-page 50
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