LAN9500 Datasheet, PDF (17/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 3-3: JTAG PINS
Num Pins
Name
JTAG Test Port
Reset
(Internal PHY
1
Mode)
Receive Data 0
(External PHY
Mode)
JTAG Test
Data Out
(Internal PHY
1
Mode)
PHY Reset
(External PHY
Mode)
JTAG Test
Clock
(Internal PHY
1
Mode)
Receive Data 1
(External PHY
Mode)
JTAG Test
Mode Select
(Internal PHY
1
Mode)
Receive Data 2
(External PHY
Mode)
JTAG Test
Data Input
(Internal PHY
1
Mode)
Receive Data 3
(External PHY
Mode)
Symbol
nTRST
RXD0
TDO
nPHY_RST
TCK
RXD1
TMS
RXD2
TDI
RXD3
Buffer
Type
IS
(PU)
Description
In internal PHY mode, this active-low pin functions
as the JTAG test port reset input.
IS
(PD)
O8
In external PHY mode, this pin functions as the
receive data 0 input from the external PHY.
In internal PHY mode, this pin functions as the
JTAG data output.
O8 In external PHY mode, this active-low pin functions
as the PHY reset output.
IS
(PU)
In internal PHY mode, this pin functions as the
JTAG test clock. The maximum operating
frequency of this clock is 25MHz.
IS
(PD)
IS
(PU)
In external PHY mode, this pin functions as the
receive data 1 input from the external PHY.
In internal PHY mode, this pin functions as the
JTAG test mode select.
IS
(PD)
IS
(PU)
In external PHY mode, this pin functions as the
receive data 2 input from the external PHY.
In internal PHY mode, this pin functions as the
JTAG data input.
IS
(PD)
In external PHY mode, this pin functions as the
receive data 3 input from the external PHY.
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DS00001875A-page 17