LAN9500 Datasheet, PDF (104/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
FIGURE 5-34:
DETAILED GPIOS 0-6 WAKE DETECTION LOGIC (LAN9500A/LAN9500AI)
IME
GPIOENn
GPIODIRn
GPIOPOLn
GPIOn
Latch
GPIODn
GPIOn_DET
GPIOn_INT clear
GPIOWKn
Note:
The IME bit is in the Hardware Configuration Register (HW_CFG). General Purpose IO Configuration Reg-
ister (GPIO_CFG) and General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE) must be set
accordingly. Diagram does not represent actual hardware implementation.
FIGURE 5-35:
DETAILED GPIO7 WAKE DETECTION LOGIC (LAN9500A/LAN9500AI)
IME
GPIOEN7
GPIODIR7
GPIOPOL7
0
1
GPIOD7
GPIO7_DET
GPIO7
GPIO7_INT clear
GPIOWK7
SUSPEND0
SUSPEND3
PHY_LINK_EN
PHY_LINK_UP
0
1
Latch
DS00001875A-page 104
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