LAN9500 Datasheet, PDF (72/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
FIGURE 5-18:
RECEIVE DATA PATH
MAC
RX_CLK
100M
PLL
Internal
MII 25MHz by 4 bits
MII
NRZI
MLT-3
Converter ^{NRZI Converter}
25MHz
by 4 bits
4B/5B 25MHz by Descrambler
Decoder
5 bits
and SIPO
125 Mbps Serial
MLT-3
DSP: Timing
recovery, Equalizer
and BLW Correction
A/D
Converter
MLT-3
Magnetics
MLT-3
RJ45
MLT-3 CAT-5
6 bit Data
5.6.2.1 100M Receive Input
The MLT-3 from the cable is fed into the PHY (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC samples
the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates 6 digital
bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that
the full dynamic range of the ADC can be used
5.6.2.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-
tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer
can restore the signal for any good-quality CAT-5 cable between 1m and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-
lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)
on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive
the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP,
selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to
extract the serial data from the received signal.
5.6.2.3 NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an
NRZI data stream.
5.6.2.4 Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel
Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once
synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
DS00001875A-page 72
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