LAN9500 Datasheet, PDF (133/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
7.3.11 AUTOMATIC FLOW CONTROL CONFIGURATION REGISTER (AFC_CFG)
Address:
02Ch
Size:
32 bits
This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause
frames and back pressure. Refer to Section 5.5.1, "Flow Control," on page 56 for more information on flow control oper-
ation.
Note: The device will not transmit pause frames or assert back pressure if the transmitter is disabled.
Bits
31:24
23:16
15:8
Description
RESERVED
Automatic Flow Control High Level (AFC_HI)
Specifies, in multiples of 64 bytes, the level at which flow control will trigger.
When this limit is reached, the chip will apply back pressure or will transmit
a pause frame, as programmed in bits [3:0] of this register.
During full-duplex operation, only a single pause frame is transmitted when
this level is reached. The pause time transmitted in this frame is programmed
in the Pause Time (FCPT) field of the Flow Control Register (FLOW),
contained in the MAC CSR space.
During half-duplex operation, each incoming frame that matches the criteria
in bits [3:0] of this register will be jammed for the period set in the
BACK_DUR field.
Automatic Flow Control Low Level (AFC_LO)
Specifies, in multiples of 64 bytes, the level at which a pause frame is
transmitted with a pause time setting of zero. When the amount of data in
the RX Data FIFO falls below this level, the pause frame is transmitted. A
pause time value of zero instructs the other transmitting device to
immediately resume transmission. The zero time pause frame will only be
transmitted if the RX Data FIFO had reached the AFC_HI level and a pause
frame was sent. A zero pause time frame is sent whenever automatic flow
control in enabled in bits [3:0] of this register.
Type
RO
R/W
R/W
Default
-
00h
00h
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DS00001875A-page 133