LAN9500 Datasheet, PDF (12/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 3-1: MII INTERFACE PINS
Num Pins
Name
Symbol
Receive Error
(Internal PHY
Mode)
RXER
1
Receive Error
(External PHY
Mode)
RXER
Transmit
Enable
(Internal PHY
Mode)
1
Transmit
Enable
(External PHY
Mode)
TXEN
TXEN
Receive Data
RXDV
Valid
(Internal PHY
Mode)
1
Receive Data
RXDV
Valid
(External PHY
Mode)
Receive Clock
(Internal PHY
Mode)
RXCLK
1
Receive Clock
(External PHY
Mode)
RXCLK
Carrier Sense
(Internal PHY
Mode)
CRS
Carrier Sense
1
(External PHY
Mode)
CRS
General
Purpose I/O 3
(Internal PHY
Mode Only)
GPIO3
Buffer
Type
IS/O8
(PD)
IS
(PD)
IS/O8
(PD)
O8
(PD)
Description
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates a
receive error in the packet.
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, this pin functions as an
output to the external PHY and indicates valid data
on TXD[3:0].
IS/O8
(PD)
IS
(PD)
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates valid
data on RXD[3:0].
IS/O8
(PD)
IS
(PD)
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, this pin is the receiver clock
input from the external PHY.
IS/O8
(PU)
IS
(PD)
IS/O8/
OD8
(PU)
In internal PHY mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 122 for additional information.
In external PHY mode, the signal on this pin is
input from the external PHY and indicates a
network carrier.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
DS00001875A-page 12
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