LAN9500 Datasheet, PDF (20/213 Pages) SMSC Corporation – USB 2.0 to 10/100 Ethernet Controller Promiscuous mode

LAN950x
TABLE 3-5: USB PINS
Num Pins
Name
USB DMINUS
1
Symbol
USBDM
USB
USBDP
1
DPLUS
External USB
USBRBIAS
1
Bias Resistor.
USB PLL
Supply
VDDUSBPLL
1
Crystal Input
XI
1
1
Crystal Output
XO
Buffer
Type
AIO
AIO
AI
P
Description
Note:
The functionality of this pin may be
swapped to USB DPLUS via the
PORT_SWAP configuration strap.
Note:
The functionality of this pin may be
swapped to USB DMINUS via the
PORT_SWAP configuration strap.
Used for setting HS transmit current level and on-
chip termination impedance. Connect to an
external 12K 1.0% resistor to ground.
This pin must be connected to VDDCORE for
proper operation.
Refer to Section 4.0, "Power Connections," on
page 24 and the device reference schematics for
additional connection information.
ICLK
OCLK
External 25 MHz crystal input.
Note:
This pin can also be driven by a single-
ended clock oscillator. When this method
is used, XO should be left unconnected
External 25 MHz crystal output.
TABLE 3-6: ETHERNET PHY PINS
Num Pins
Name
Symbol
Ethernet TX
1
Data Out
Negative
TXN
Ethernet TX
TXP
1
Data Out
Positive
Ethernet RX
1
Data In
Negative
RXN
Ethernet RX
1
Data In
Positive
RXP
PHY Interrupt
(Internal PHY
Mode)
nPHY_INT
1
PHY Interrupt
(External PHY
Mode)
nPHY_INT
Buffer
Type
AIO
AIO
AIO
AIO
O8
IS
(PU)
Description
The transmit data outputs may be swapped
internally with receive data inputs when Auto-MDIX
is enabled.
The transmit data outputs may be swapped
internally with receive data inputs when Auto-MDIX
is enabled.
The receive data inputs may be swapped internally
with transmit data outputs when Auto-MDIX is
enabled.
The receive data inputs may be swapped internally
with transmit data outputs when Auto-MDIX is
enabled.
In internal PHY mode, this pin can be configured
to output the internal PHY interrupt signal.
Note: The internal PHY interrupt signal is
active-high.
In external PHY mode, the active-low signal on this
pin is input from the external PHY and indicates a
PHY interrupt has occurred.
DS00001875A-page 20
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