82371FB Datasheet, PDF (99/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
Each PRD entry is 8 bytes in length. PRDs must be aligned on 64-Kbyte boundaries. The first 4 bytes specify
the byte address of a physical memory region. The next two bytes specify the count of the region in bytes
(64-Kbyte limit per region). A value of zero in these two bytes indicates 64 Kbytes. Bit 7 of the last byte
indicates the end of the table (EOT). Bus master operation terminates when the last descriptor has been
retired.
Main Memory
Byte 3
Byte 2
Byte 1
Byte 0
Memory Region Physical Base Address [31:1] 0
EOT
Reserved
Byte Count [15:1]
0
Memory
Region
051910_3.drw
051910
Figure 5. Physical Region Descriptor Table Entry
NOTE
The memory region specified by the descriptor cannot straddle a 64-Kbyte boundary. This means that
the byte count can be limited to 64 Kbytes and the incrementer for the current address register need
only extend from bit 1 to bit 15. Also, the total sum of the descriptor byte counts must be equal to or
greater than the size of the disk transfer request. If greater than the disk transfer request, the driver
must terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register
to 0) when the drive issues an interrupt to signal transfer completion.
Operation
To initiate a bus master transfer between memory and an IDE DMA slave device, the following steps are
required:
1. Software prepares a PRD Table in main memory. Each PRD is 8 bytes long and consists of an address
pointer to the starting address and the transfer count of the memory buffer to be transferred. In any given
PRD Table, two consecutive PRDs are offset by 8-bytes and are aligned on a 4-byte boundary.
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer Register . The
direction of the data transfer is specified by setting the Read/Write Control bit. Clear the Interrupt bit and
Error bit in the Status register.
3. Software issues the appropriate DMA transfer command to the disk device.
4. Engage the bus master function by writing a 1 to the Start bit in the Bus Master IDE Command Register
for the appropriate channel. The first entry in the PRD table is fetched by the PIIX. The channel remains
masked until the first descriptor is loaded.
5. The controller transfers data to/from memory responding to DMA requests from the IDE device.
6. At the end of the transfer, the IDE device signals an interrupt.
7. In response to the interrupt, software resets the Start/Stop bit in the command register. It then reads the
controller status and then the drive status to determine if the transfer completed successfully.
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