82371FB Datasheet, PDF (54/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
2.4.2. DIDDEVICE IDENTIFICATION REGISTER (Function 2) (PIIX3)
Address Offset:
Default Value:
Attribute:
02−03h
7020h
Read Only
The DID Register contains the device identification number. This register, along with the VID Register, define
the PIIX. Writes to this register have no effect.
Bit
Description
15:0 Device Identification Number. This is a 16-bit value assigned to the PIIX3.
2.4.3. PCICMDCOMMAND REGISTER (Function 2) (PIIX3)
Address Offset:
Default Value:
Attribute:
04−05h
00h
Read/Write
This register controls access to the I/O space registers.
Bit
15:10
9
8:5
4
3
2
1
0
Description
Reserved. Read 0.
Fast Back to Back Enable (FBE). (Not Implemented) This bit is hardwired to 0.
Reserved. Read as 0.
Memory Write and Invalidate Enable (MWI). (Not Implemented) This bit is hardwired to
0.
Special Cycle Enable (SCE). (Not Implemented) This bit is hardwired to 0.
Bus Master Enable (BME). This bit controls the PIIX3’s ability to act as a master on the
PCI bus for the host controller transfers. A value of 0 disables the device from generating
PCI accesses. A value of 1 allows the device to behave as a USB host controller bus
master. This bit must be set to 1 before serial bus transactions can start.
Memory Space Enable (MSE). (Not Implemented) This bit is hardwired to 0.
I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the I/O
space registers. If this bit is set, access to the host controller IO registers is enabled. The
base register for the I/O registers must be programmed before this bit is set.
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