82371FB Datasheet, PDF (6/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
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3.1. Memory and I/O Address Map ........................................................................................................... 89
3.1.1. I/O Accesses ............................................................................................................................... 89
3.1.2. Memory Address Map ................................................................................................................. 89
3.1.3. BIOS MEMORY........................................................................................................................... 90
3.2. PCI Interface ...................................................................................................................................... 90
3.2.1. TRANSACTION TERMINATION ................................................................................................. 90
3.2.2. PARITY SUPPORT ..................................................................................................................... 91
3.2.3. PCI ARBITRATION ..................................................................................................................... 91
3.3. ISA Interface ...................................................................................................................................... 92
3.4. DMA Controller................................................................................................................................... 93
3.4.1. TYPE F TIMING .......................................................................................................................... 94
3.4.2. ISA REFRESH CYCLES ............................................................................................................. 94
3.5. PCI Local Bus IDE ............................................................................................................................. 95
3.5.1. ATA REGISTER BLOCK DECODE ............................................................................................. 96
3.5.2. ENHANCED TIMING MODES ..................................................................................................... 97
3.5.2.1. Back-To-Back PIO IDE Transactions.................................................................................... 98
3.5.2.2. IORDY Masking .................................................................................................................... 98
3.5.2.3. PIO 32 Bit IDE Data Port Mode ............................................................................................ 98
3.5.3. BUS MASTER FUNCTION.......................................................................................................... 98
3.6. Universal Serial Bus Host Controller (PIIX3 only) ............................................................................. 100
3.7. Interval Timer ................................................................................................................................... 102
3.8. Interrupt Controller ........................................................................................................................... 103
3.8.1. PROGRAMMING THE ICWs/OCWs ......................................................................................... 104
3.8.2. EDGE AND LEVEL TRIGGERED MODE .................................................................................. 104
3.8.3. INTERRUPT STEERING........................................................................................................... 104
3.9. Stand-Alone IOAPIC Support (PIIX3) ............................................................................................... 105
3.10. INTR Signaling with Pentium® processor Local APIC in Virtual Wire Mode ................................... 106
3.11. X-Bus Peripheral Support............................................................................................................... 107
3.12. Power Management ....................................................................................................................... 108
3.12.1. SMM MODE ............................................................................................................................ 109
3.12.2. SMI SOURCES ....................................................................................................................... 109
3.12.3. CLOCK CONTROL.................................................................................................................. 110
3.13. Reset Support ................................................................................................................................ 110
3.13.1. HARDWARE STRAPPING OPTIONS ..................................................................................... 111
4.0. PINOUT AND PACKAGE INFORMATION .......................................................................................... 112
4.1. Pinout............................................................................................................................................... 112
4.2. PACKAGE DIMENSIONS ................................................................................................................ 117
5.0. TESTABILITY (PIIX/PIIX3) .................................................................................................................. 118
5.1. Test Mode Description ..................................................................................................................... 118
5.2. NAND Tree Mode............................................................................................................................. 118
5.3. Tri-state Mode.................................................................................................................................. 122
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