82371FB Datasheet, PDF (122/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
Figure 13 is a schematic of the NAND tree circuitry.
MDRQ1
MDRQ0
RSTDRV
DREQ1
DACK1#
DACK1#
NAND CHAIN
SELECT
E
KBCCS#
XOE#
XDIR
XDIR
NAND CHAIN
SELECT
051917_3.drw
Figure 13. NAND Tree Circuitry
051917
NAND Tree Timing Requirements
Allow 500 ns for the input signals to propagate to the NAND tree outputs (input-to-output propagation delay
specification).
5.3. Tri-state Mode
The TESTIN# signal must be 0 and IRQ’s 7, 6, and 5 must be 1 to enter the tri-state test mode. When in the
tri-state test mode, all outputs and bi-directional pins are tri-stated, including the NAND tree outputs.
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