82371FB Datasheet, PDF (14/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Signal Name
SA[7:0],
SA[19:8]/
DD[11:0]
Type
I/O
I/O
I/O
SBHE#/
I/O
DD12
I/O
MEMCS16#
od
MEMR#
I/O
MEMW#
I/O
SMEMR#
O
SMEMW#
O
ZEROWS#
I
SD[15:0]
I/O
Description
SYSTEM ADDRESS BUS: These bi-directional address lines define the
selection with the granularity of one byte within the one-Mbyte section of
memory defined by the LA[23:17] address lines. The address lines
SA[19:17] that are coincident with LA[19:17] are defined to have the same
values as LA[19:17] for all memory cycles. For I/O accesses, only SA[15:0]
are used.
SYSTEM BYTE HIGH ENABLE: SBHE# indicates, when asserted, that a
byte is being transferred on the upper byte (SD[15:8]) of the data bus.
SBHE# is negated during refresh cycles.
MEMORY CHIP SELECT 16: MEMCS16# is a decode of LA[23:17]
without any qualification of the command signal lines. ISA slaves that are
16-bit memory devices drive this signal low. The PIIX/PIIX3 drives this
signal low during ISA master to DRAM Cycles.
MEMORY READ: MEMR# is the command to a memory slave that it may
drive data onto the ISA data bus. This signal is also driven by the
PIIX/PIIX3 during refresh cycles.
MEMORY WRITE: MEMW# is the command to a memory slave that it
may latch data from the ISA data bus.
STANDARD MEMORY READ: The PIIX/PIIX3 asserts SMEMR# to
request an ISA memory slave to drive data onto the data lines. If the
access is below 1 Mbyte (00000000–000FFFFFh) during DMA compatible,
PIIX/PIIX3 master, or ISA master cycles, the PIIX/PIIX3 asserts SMEMR#.
SMEMR# is a delayed version of MEMR#.
STANDARD MEMORY WRITE: The PIIX/PIIX3 asserts SMEMW# to
request an ISA memory slave to accept data from the data lines. If the
access is below 1 Mbyte (00000000–000FFFFFh) during DMA compatible,
PIIX/PIIX3 master, or ISA master cycles, the PIIX/PIIX3 asserts
SMEMW#. SMEMW# is a delayed version of MEMW#.
ZERO WAIT-STATES: An ISA slave asserts ZEROWS# after its address
and command signals have been decoded to indicate that the current
cycle can be shortened. A 16-bit ISA memory cycle can be reduced to two
SYSCLKs. An 8-bit memory or I/O cycle can be reduced to three
SYSCLKs. ZEROWS# has no effect during 16-bit I/O cycles.
SYSTEM DATA: SD[15:0] provide the 16-bit data path for devices residing
on the ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0]
correspond to the low order byte. SD[15:0] are undefined during refresh.
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