82371FB Datasheet, PDF (66/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
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2.5.1.10. DMA Clear Byte Pointer Register
I/O Address:
Default Value:
Attribute:
Channels 0-3—00Ch; Channels 4-7—0D8h
All bits undefined
Write Only
Writing to this register executes the Clear Byte Pointer Command. This command is executed prior to
reading/writing a new address or word count to the DMA. The command initializes the byte pointer flip-
flop to a known state so that subsequent accesses to register contents address upper and lower bytes
in the correct sequence. The Clear Byte Pointer Command (or CPURST or the Master Clear
Command) clears the internal latch used to address the upper or lower byte of the 16-bit Address and
Word Count Registers.
Bit
Description
7:0
Clear Byte Pointer. No specific pattern. Command enabled with a write to the I/O port
address.
2.5.1.11. DMC—DMA Master Clear Register
I/O Address:
Default Value:
Attribute:
Channel 0-3—00Dh; Channel 4-7—0DAh
All bits undefined
Write Only
This software instruction has the same effect as the hardware Reset.
Bit
Description
7:0
Master Clear. No specific pattern. Command enabled with a write to the I/O port address
2.5.1.12. DCLM—DMA Clear Mask Register
I/O Address:
Default Value:
Attribute:
Channel 0-3—00Eh; Channel 4-7—0DCh
All bits undefined
Write Only
This command clears the mask bits of all four channels, enabling them to accept DMA requests.
Bit
Description
7:0
Clear Mask Register. No specific pattern. Command enabled with a write to the I/O port
address.
2.5.2. TIMER/COUNTER REGISTER DESCRIPTION
2.5.2.1.
TCW—Timer Control Word Register
I/O Address:
Default Value:
Attribute:
043h
All bits undefined
Write Only
The Timer Control Word Register specifies the counter selection, the operating mode, the counter byte
programming order and size of the count value, and whether the counter counts down in a 16-bit or binary-
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