82371FB Datasheet, PDF (32/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Bit
2
1
0
Description
Bus Master Enable (BME). (Not Implemented) The PIIX/PIIX3 does not support disabling
its bus master capability. This bit is hardwired to 1.
Memory Access Enable (MAE). (Not Implemented) The PIIX/PIIX3 does not support
disabling access to main memory. This bit is hardwired to 1.
I/O Space Access Enable (IOSE). The PIIX/PIIX3 does not support disabling its response to
PCI I/O cycles. This bit is hardwired to 1.
2.2.4. PCISTS—PCI DEVICE STATUS REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
06–07h
0200h
Read/Write Clear
The PCISTS Register reports the occurrence of a PCI master-abort by the PIIX/PIIX3 or a PCI target-abort
when the PIIX/PIIX3 is a master. The register also indicates the PIIX/PIIX3 DEVSEL# signal timing.
Bit
Description
15
Detected Parity Error (PERR). (Not Implemented) Read as 0.
14
PIIX: Signaled SERR# Status (SERRS). (Not Implemented) Read as 0.
PIIX3: Signaled SERR# Status (SERRS)—R/WC. When the PIIX3 asserts the SERR#
signal, this bit is set to 1. Software sets this bit to a 0 by writing a 1 to it
13
Master-Abort Status (MA)—R/WC. When the PIIX, as a master (for the ISA bridge function),
generates a master-abort, MA is set to a 1. Software sets MA to 0 by writing a 1 to this bit
location.
12
Received Target-Abort Status (RTA)—R/WC. When the PIIX/PIIX3 is a master on the PCI
Bus (for the ISA bridge function) and receives a target-abort, this bit is set to a 1. Software
sets RTA to 0 by writing a 1 to this bit location.
11
Signaled Target-Abort Status (STA)—R/WC. This bit is set when the PIIX/PIIX3 ISA bridge
function is targeted with a transaction that the PIIX/PIIX3 terminates with a target abort.
Software sets STA to 0 by writing a 1 to this bit location.
10:9 DEVSEL# Timing Status (DEVT)—RO. The PIIX/PIIX3 always generates DEVSEL# with
medium timing for ISA functions. Thus, DEVT=01. This DEVSEL# timing does not include
Configuration cycles.
8
PERR# Response. (Not Implemented) Read as 0.
7
Fast Back to Back—RO. This bit indicates to the PCI Master that PIIX/PIIX3 as a target is
capable of accepting fast back-to-back transactions.
6:0
Reserved. Read as 0s.
32