82371FB Datasheet, PDF (56/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
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2.4.6. CLASSCCLASS CODE REGISTER (Function 2) (PIIX3)
Address Offset:
Default Value:
Attribute:
09−0Bh
010180h
Read Only
This register contains the device programming interface information related to the Sub-Class Code and Base
Class Code definition for the PIIX3 (function 2). This register also identifies the Base Class Code and the
function sub-class in relation to the Base Class Code.
Bit
Description
23:1 Base Class Code (BASEC). 0Ch=Universal Serial Bus controller.
6
15:8 Sub-Class Code (SCC). 03h=Universal Serial Bus Host Controller..
7:0
Programming Interface (PI). 00h=Capable of Universal Serial Bus operation.
2.4.7. MLTMASTER LATENCY TIMER REGISTER (Function 2) (PIIX3)
Address Offset:
Default Value:
Attribute:
0Dh
00h
Read/Write
MLT is an 8-bit register that controls the amount of time (in terms of PCI clocks) the USB module can do
transactions on the PCI bus. The count value is an 8-bit quantity, however MLT[3:0] are reserved and
assumed to be 0 when determining the count value. MLT is used when the USB module becomes the PCI
bus master and is cleared and suspended when PIIX3 is not asserting FRAME#. When PIIX3 asserts
FRAME#, the counter is enabled and begins counting. If the serial bus module finishes its transaction before
count is expired the MLT value is ignored. If the count expires before the transaction completes, PIIX3
initiates a transaction termination as soon as the current transaction is completed.. The number of clocks
programmed in the MLT represents the guaranteed time slice (measured in PCI clocks) allotted to PIIX3,
after which it must surrender the bus as soon as the current transaction is completed. The default value of
MLT is 00h.
Bit
Description
7:4 Master Latency Counter Value. PIIX3 initiated PCI cycles (including multiple transactions) can
last indefinitely as long as PHLDA# remains active. However, if PHLDA# is negated after a
transaction is initiated, PIIX3 limits the duration of the transactions to the number of PCI bus
clocks specified by this field.
3:0 Reserved.
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