82371FB Datasheet, PDF (37/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

E
82371FB (PIIX) AND 82371SB (PIIX3)
Bit
3
2
1
0
Description
ISA/DMA Lower BIOS Forwarding Enable. 1=Enable (forwarded to PCI, if XBCS Register
bit 6=0); 0=Disable (contained to ISA). Note that If the XBCS Register bit 6=1, ISA/DMA
accesses in this region are always contained to ISA.
PIIX: Reserved
PIIX3: A,B Segment Forwarding Enable. 1=Enable (forward to PCI), 0 = Disable (default,
contain to ISA). When enabled, this bit allows ISA Master and DMA memory accesses to
A0000h−BFFFFh range to be forwarded to PCI. When disabled, these accesses are
contained to ISA.
ISA/DMA 512–640-Kbyte Region Forwarding Enable. 1=Enable (forwarded to PCI);
0=Disable (contained to ISA).
Reserved
2.2.12. MSTAT—MISCELLANEOUS STATUS REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
6B–6Ah
Undefined
PIIX: Read/Write (bits [1:0] are read only)
PIIX3: Read/Write Clear(bits 1 is read only)
This register provides miscellaneous status and control functions.
Bit
15
14:8
7
Description
PIIX: Reserved.
PIIX3: SERR# Generation Due To Delayed TransactionR/WC. PIIX3 sets this bit to a 1
when it generates SERR# due to a delayed transaction. Software sets this bit to a 0 by writing
a 1 to it.
Reserved.
PIIX: Reserved
PIIX3: NB Retry Enable (NBRE)--R/W, 1=Enable, 0 = Disable (default). This bit, when
enabled, causes the PIIX3 to retry, without initiating a delayed transaction, CPU initiated,
non-LOCK#, PCI cycles. No delayed transactions to PIIX3 may currently be pending and
passive release must be active. Delayed Transactions and Passive Release must both be
enabled via the DLC Register (function 0, offset 82h). When disabled, the PIIX3 accepts
these cycles as normal, which may include retry with initiation of a delayed transaction.
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