82371FB Datasheet, PDF (97/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
Table 13. IDE Legacy I/O port definition: COMMAND BLOCK (CS1x# chip select)
IO Offset
Register Function (Read / Write)
Access
00h
Data
R/W
01h
Error/Features
R/W
02h
Sector Count
R/W
03h
Sector Number
R/W
04h
Cylinder Low
R/W
05h
Cylinder High
R/W
06h
Drive/Head
R/W
07h
Status/Command
R/W
The Data Register is accessed as a 16-bit register for PIO transfers (except for ECC bytes). All other
registers are accessed as 8-bit quantities.
Table 14. IDE Legacy I/O port definition: CONTROL BLOCK (CS3x# chip select)
IO Offset
Register Function (Read / Write)
Access
00h
Reserved
reserved
01h
Reserved
reserved
02h
Alt Status/Device control
R/W
03h
Forward to ISA (Floppy)
R/W
The PIIX/PIIX3 claims all accesses to these ranges. The byte enables do not have to be externally decoded
to assert DEVSEL#. Accesses to byte 3 of the Control Block are forwarded to ISA where the floppy disk
controller responds.
Each of the two drives (drive 0 or 1) on a cable implement separate ATA register files. To determine the
targeted drive, the PIIX/PIIX3 shadows the value of bit 4 (drive bit) of byte 6 (drive/head register) of the ATA
command block (CS1x#) for each of the two IDE connectors (primary and secondary).
3.5.2. ENHANCED TIMING MODES
The PIIX/PIIX3 includes fast timing modes. The fast timing modes can be enabled only for the IDE data ports.
All other transactions to the IDE registers are run in single transaction mode with compatible timings.
Up to 2 IDE devices may be attached per IDE connector (drive 0 and drive 1). For each connector in a PIIX
system, only one fast timing mode may be specified (via the IDETIM Register). This mode can be applied to
drive 0, drive 1, or both. Transactions targeting the other drive will use compatible timing.
For the PIIX3, the IDETIM and SIDETIM Registers permit different timing modes to be programmed for drive
0 and drive 1 of the same connector.
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