82371FB Datasheet, PDF (60/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Bit
Description
5
A20Gate Pass-through Enable (A20PTEN)R/W. 1=Enable A20GATE pass-through
sequence. 0=Disable (default). When enabled, the logic will pass-through the following
A20GATE command sequence:
Cycle
Address Data
Write
64h
Write
60h
Read
64h
Write
64h
D1h ( 1 or more) (Starts the Sequence)
xxh
N/A ( 0 or more)
FFh ( Standard End of A20GATE Pass-through Sequence)
Any deviation in the above sequence causes the host controller to immediately exit the
sequence and return to standard operation, performing an I/O trap and generating an SMI# if
appropriate enable bits are set.
When enabled, SMI# is not generated during the sequence, even if the various enable bits are
set. Note that during a pass-through sequence, the above status bits are not set for the I/O
accesses that are part of the sequence.
4
Trap/SMI ON IRQ Enable (USBSMIEN)R/W. 1=Enable SMI# generation on USB IRQ.
0=Disable (default).
3
Trap/SMI On 64h Write Enable (64WEN)R/W. 1=Enable I/O Trap and SMI# generation on
port 64h write.
0=Disable (default).
2
Trap/SMI On 64h Read Enable (64REN)R/W. 1=Enable I/O Trap and SMI# generation on
port 64h read.
0=Disable (default).
1
Trap/SMI On 60h Write Enable (60WEN)R/W. 1=Enable I/O Trap and SMI# generation on
port 60h write.
0=Disable (default).
0
Trap/SMI On 60h Read Enable (60REN)R/W. 1 = Enable I/O Trap and SMI# generation on
port 60h read.
0=Disable (default).
60