82371FB Datasheet, PDF (83/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

E
82371FB (PIIX) AND 82371SB (PIIX3)
Bit
3
2
1
0
Description
PCI Bus Error. The Host Controller sets this bit to 1 when a serious error occurs during a
PCI access involving the Host Controller module. PCI conditions that set this bit to 1 include
PCI Master Abort and PCI Target Abort. When this error occurs, the Host Controller clears
the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs.
A hardware reset is generated to the system.
Resume Received. The Host Controller sets this bit to 1 when it receives a “RESUME”
signal from a USB device. This is only valid if the Host Controller has been in a suspended
state (bit 3 of Command register = 1).
USB Error Interrupt. The Host Controller sets this bit to 1 when completion of a USB
transaction results in an error condition (e.g., error counter underflow). If the Transfer
Descriptor (TD) data structure on which the error interrupt occurred also had its IOC bit set,
both this bit and Bit 0 are set.
USB Interrupt (USBINT). The Host Controller sets this bit to 1 when the cause of an
interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is detected (actual length field
in TD is less than maximum length field in TD), and short packets are enabled in that TD.
2.8.3. USBINTRUSB Interrupt Enable Register
I/O Address:
Default Value:
Attribute:
size:
Base + (04−05h)
0000h
Read/Write
16 bits
This register enables/disables reporting of the corresponding interrupt to the software. When a bit is set and
the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors (Host Controller
Processor Error- bit 4, USBSTS Register) cannot be disabled. Interrupt sources that are disabled in this
register still appear in the Status Register to allow the software to poll for events.
Bit
Description
15:4 Reserved.
3
Short Packet Interrupt Enable. 1=Enabled. 0=Disabled.
2
Interrupt On Complete (IOC) Enable. 1= Enabled. 0=Disabled.
1
Resume Enable. 1= Enabled. 0=Disabled.
0
Timeout/CRC Enable. 1= Enabled. 0=Disabled.
2.8.4. FRNUMFrame Number Register
I/O Address:
Default Value:
Attribute:
Size:
Base + (06−07h)
0000h
Read/Write (Writes must be Word Writes)
16 bits
Bits [10:0] of this register contain the current frame number and this number is included in the frame SOF
packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are used to
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