82371FB Datasheet, PDF (68/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Bit
Description
3
Counter 2 Select. When bit 3=1, Counter 2 is selected for the latch command selected with
bits 4 and 5. When bit 3=0, status and/or count will not be latched.
2
Counter 1 Select. When bit 2=1, Counter 1 is selected for the latch command selected with
bits 4 and 5. When bit 2=0, status and/or count will not be latched.
1
Counter 0 Select. When bit 1=1, Counter 0 is selected for the latch command selected with
bits 4 and 5. When bit 1=0, status and/or count will not be latched.
0
Reserved. Must be 0.
Counter Latch Command
The Counter Latch Command latches the current count value at the time the command is received. If a
Counter is latched once and then, some time later, latched again before the count is read, the second
Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch
Command was issued. If the counter is programmed for two byte counts, two bytes must be read. The two
bytes do not have to be read successively (read, write, or programming operations for other counters may be
inserted between the reads). Note that the Timer Counter Register bit definitions are different during the
Counter Latch Command than for a normal Timer Counter Register write. Note that, If a counter is
programmed to read/write two-byte counts, a program must not transfer control between reading the first and
second byte to another routine that also reads from that same counter. Otherwise, an incorrect count will be
read.
Bit
Description
7:6
Counter Selection. Bits 6 and 7 are used to select the counter for latching.
Bit[7:6]
00
01
10
11
Function
latch counter 0 select
latch counter 1 select
latch counter 2 select
Read Back Command select
5:4
Counter Latch Command. When bits[5:4]=00, the Counter Latch Command is selected
during a write to the Timer Control Word Register. Following the Counter Latch Command, I/O
reads from the selected counter’s I/O addresses produce the current latched count.
3:0
Reserved. Must be 0.
2.5.2.2.
Interval Timer Status Byte Format Register
I/O Address:
Default Value:
Attribute:
Counter 0—040h; Counter 1—041h; Counter 2—042h
Bits[6:0]=X; Bit 7=0
Read Only
Each counter's status byte can be read following an Interval Timer Read Back Command. If latch status is
chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the
counter's Counter Access Ports Register returns the status byte.
Bit
Description
7
Counter OUT Pin State. 1=Pin is 1; 0=Pin is 0.
68