82371FB Datasheet, PDF (30/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
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Table 6. PCI Bus Master IDE I/O Registers
Offset
From Base
Address
Mnemonic
Register
00h
BMICP
Bus Master IDE Command (primary)
01h
—
Reserved
02h
BMISP
Bus Master IDE Status (primary)
03h
—
Reserved
04–07h
BMIDTPP
Bus Master IDE Descriptor Table Pointer (primary)
08h
BMICS
Bus Master IDE Command (secondary)
09h
—
Reserved
0Ah
BMISS
Bus Master IDE Status (secondary)
0Bh
—
Reserved
0C–0Fh
BMIDTPS
Bus Master IDE Descriptor Table Pointer (secondary)
NOTE:
The base address is programmable via the BMIBA Register (20−23h; function 1)
Register
Access
R/W
—
R/WC
—
R/W
R/W
—
R/WC
—
R/W
I/O Address
Base + (00−01h)
Base + (02−03h)
Base + (04−05h)
Base + (06−07h)
Base + (08−0Bh)
Base + 0Ch
Base + (10−11h)
Base + (12−13h)
Table 7. USB Host/Controller I/O Registers
Mnemonic
Register Description
USBCMD
USBSTS
USBINTR
FRNUM
FRBASEADD
SOFMOD
PORTSC1
PORTSC2
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start Of Frame Modify
Port 1 Status/Control
Port 2 Status/Control
Register
Access
R/W
R/WC
R/W
R/W**
R/W
R/W
R/WC**
R/WC**
** NOTE: These registers are WORD writeable only. Byte writes to these registers have unpredictable
effects.
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