82371FB Datasheet, PDF (74/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
2.5.3.9.
ELCR1—Edge/Level Triggered Register
I/O Address:
Default Value:
Attribute:
INT CNTRL-1—4D0h
00h
Read/Write
ELCR1 register allows IRQ3 - IRQ7 to be edge or level programmable on an interrupt by interrupt basis.
IRQ0, IRQ1 and IRQ2 are not programmable and are always edge sensitive.
Bit
Description
7
IRQ7 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
6
IRQ6 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
5
IRQ5 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
4
IRQ4 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
3
IRQ3 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
2:0
Reserved. Must be 0.
2.5.3.10. ELCR2—Edge/Level Triggered Register
I/O Address:
Default Value:
Attribute:
INT CNTRL-2—4D1h
00h
Read/Write
ELCR2 register allows IRQ[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis.
Note that, IRQ[13,8#] are not programmable and are always edge sensitive.
Bit
Description
7
IRQ15 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
6
IRQ14 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
5
Reserved. Must be 0.
4
IRQ12 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
3
IRQ11 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
2
IRQ10 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
1
IRQ9 ECL. 0 = edge triggered mode; 1 = level sensitive mode.
0
Reserved. Must be 0.
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