82371FB Datasheet, PDF (94/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
NOTE
1. For type F timing mode DMA transfers, the channel must be programmed with a memory range that will
be forwarded to PCI. This means that if BIOS detects that ISA memory is used in the system (i.e., that
the top of memory reported to the operating system is higher than the top of memory programmed in the
PIIX/PIIX3 Top of Memory register), the BIOS should not enable type F for any channel.
2. For the PIIX in External DMA mode (selected via a strapping option on the TC signal), the PIIX tri-states
the AEN, TC, and DACK[7:5, 3:0]# signals, and also forwards PCI master I/O accesses to location 0000h
to ISA.
3.4.1. TYPE F TIMING
Type F cycles occur back to back at a minimum repetition rate of 3 SYSCLKs. The type F cycles are always
performed using the 4 byte DMA buffer. Type F transfers and the use of the DMA buffer are invoked in the
MBDMAx Register. The 4 byte buffer and the type F timings may be used only when the DMA channel is
programmed to increment mode (not decrement), and cannot be used when the channel is programmed to
operate in block mode (single transfer mode and demand mode are legal). In addition, verify transfers are not
supported with type F DMA.
The PIIX device does not support Type FDMA write timings on DMA channels, only AT compatible mode
timings should be used for writes. Type FDMA read timings on DMA channels are supported by the PIIX.
3.4.2. ISA REFRESH CYCLES
Refresh cycle requests are generated by two sources—the refresh controller inside the PIIX/PIIX3
component or ISA Bus masters other than the PIIX. In both cases, the PIIX/PIIX3 generates the ISA memory
refresh. The PIIX/PIIX3 enables address lines SA[7:0]. Thus, when MEMR# goes active, the entire ISA
system memory is refreshed at one time. Memory slaves on the ISA Bus must not drive any data onto the
data bus during the refresh cycle. The PIIX/PIIX3 maintains a four deep buffer to record internally generated
refresh requests that have not been serviced. Counter 1 in the timer register set should be programmed to
provide a request for refresh about every 15µs.
Initiated Refresh Cycle
The PIIX/PIIX3 asserts REFRESH# to indicate a refresh cycle and then drives the address lines SA[7:0] onto
the ISA Bus and generates MEMR# and SMEMR#. The PIIX/PIIX3 drives AEN and BALE high for the entire
refresh cycle. The memory device may extend this refresh cycle by pulling IOCHRDY low.
ISA Bus refresh cycles are completely decoupled from DRAM Refresh. Transactions driven by PCI masters
that target ISA or IDE resources while refresh is active are held off with wait states until the refresh is
complete.
ISA Master Initiated Refresh Cycle
If an ISA Bus master holds the ISA Bus longer than 15 µsec, the ISA master must initiate memory refresh
cycles. If the ISA Bus master initiates a refresh cycle before it relinquishes the bus, it floats the address lines
and control signals and asserts the REFRESH# to the PIIX. The PIIX/PIIX3 drives address lines SA[7:0] and
MEMR# onto the ISA Bus. BALE is driven high and AEN is driven low for the entire refresh cycle.
If the ISA Bus master holding the bus does not a generate a refresh request and the PIIX's internal refresh
request is not serviced within the normal 15 µs, a refresh queue counter is incremented. The counter records
up to four incomplete refresh cycles, which are all executed as soon as PIIX/PIIX3 gets the ISA Bus.
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