82371FB Datasheet, PDF (10/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Signal Name
TRDY#
IRDY#
STOP#
IDSEL
Type
I/O
(s/t/s)
I/O
(s/t/s)
I/O
(s/t/s)
I
DEVSEL#
PAR
I/O
(s/t/s)
O
SERR#
I
PHOLD#
O
PHLDA#
I
Description
TARGET READY: Asserted when the target is ready for a data transfer.
INITIATOR READY: Asserted when the initiator is ready for a data
transfer.
STOP: Asserted by the target to request the master to stop the current
transaction.
INITIALIZATION DEVICE SELECT: IDSEL is used as a chip select during
configuration read and write transactions.
DEVICE SELECT: The PIIX/PIIX3 asserts DEVSEL# to claim a PCI
transaction through positive or subtractive decoding.
CALCULATED PARITY SIGNAL: PAR is "even" parity and is calculated
on 36 bits—AD[31:0] plus C/BE[3:0]#.
SYSTEM ERROR: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
PIIX/PIIX3 can be programmed to generate a non-maskable interrupt
(NMI) to the CPU.
PCI HOLD: The PIIX/PIIX3 asserts this signal to request the PCI Bus.
The PIIX3 implements the passive release mechanism by toggling PHOLD#
inactive for one PCICLK.
PCI HOLD ACKNOWLEDGE: This signal is asserted to grant the PCI bus
to the PIIX/PIIX3.
1.2. Motherboard I/O Device Interface Signals
Signal Name
MDRQ[1:0]
(PIIX Only)
MDAK[1:0]#
(PIIX Only)
Type
I
O
Description
MOTHERBOARD DEVICE DMA REQUEST: These signals can be
connected internally to any of DREQ[3:0,7:5]. Each pair of request/
acknowledge signals is controlled by a separate register. Each signal
can be configured as steerable interrupts for motherboard devices.
MOTHERBOARD DEVICE DMA ACKNOWLEDGE: These signals
can be connected internally to any of DACK[3:0,7:5]. Each pair of
request/ acknowledge signals is controlled by a separate register.
Each signal can be configured as steerable interrupts for motherboard
devices.
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