82371FB Datasheet, PDF (73/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

E
82371FB (PIIX) AND 82371SB (PIIX3)
Bit
Description
2:0
Interrupt Level Select (L2, L1, L0). L2, L1, and L0 determine the interrupt level acted upon
when the SL bit is active (bit 6). When the SL bit is inactive, bits [2:0] do not have a defined
function; programming L2, L1 and L0 to 0 is sufficient in this case.
Bit[2:0]
000
001
010
011
Interrupt Level
IRQ 0(8)
IRQ 1(9)
IRQ 2(10)
IRQ 3(11)
Bit[2:0]
100
101
110
111
Interrupt Level
IRQ 4(12)
IRQ 5(13)
IRQ 6(14)
IRQ 7(15)
2.5.3.8.
OCW3—Operational Control Word 3 Register
I/O Address:
Default Value:
Attribute:
INT CNTRL-1—020h; INT CNTRL-2—0A0h
Bit[6,0]=0; Bit[7,4:2]=Undefined; Bit[5,1]=1
Read/Write
OCW3 serves three important functions—Enable Special Mask Mode, Poll Mode control, and IRR/ISR
register read control.
Bit
Description
7
Reserved. Must be 0.
6
Special Mask Mode (SMM). If ESMM=1 and SMM=1, the interrupt controller enters Special
Mask Mode. If ESMM=1 and SMM=0, the interrupt controller is in normal mask mode. When
ESMM=0, SMM has no effect.
5
Enable Special Mask Mode (ESMM). 1=Enable SMM bit; 0=Disable SMM bit.
4:3
OCW3 Select. Must be programmed to 01 selecting OCW3.
2
Poll Mode Command. 0=Disable Poll Mode Command. When bit 2=1, the next I/O read to
the interrupt controller is treated as an interrupt acknowledge cycle indicating highest priority
request..
1:0
Register Read Command. Bits [1:0] provide control for reading the In-Service Register (ISR)
and the Interrupt Request Register (IRR). When bit 1=0, bit 0 doesl not affect the register read
selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If
bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the
default OCW3 port address read will be "read IRR". To retain the current selection (read ISR or
read IRR), always write a 0 to bit 1 when programming this register. The selected register can
be read repeatedly without reprogramming OCW3. To select a new status register, OCW3
must be reprogrammed prior to attempting the read.
Bit[1:0]
00
01
10
11
Function
No Action
No Action
Read IRQ Register
Read IS Register
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