82371FB Datasheet, PDF (77/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

E
82371FB (PIIX) AND 82371SB (PIIX3)
Bit
Description
4
Refresh Cycle Toggle—RO. The Refresh Cycle Toggle signal toggles from either 0 to 1 or 1
to 0 following every refresh cycle. When writing to port 061h, bit 4 must be a 0.
3
IOCHK# NMI Enable—R/W. 1=Clear and disable; 0=Enable IOCHK# NMIs.
2
PCI SERR# Enable—R/W. 1=Clear and Disable; 0=Enable.
For the PIIX3, the SERR# signal can be for a special protocol between the host-to-PCI bridge
and the PIIX3 (see MSTAT Register description, 6B−6Ah, function 0).
1
Speaker Data Enable—R/W. 0=SPKR output is 0; 1= the SPKR output is the Counter 2 OUT
signal value.
0
Timer Counter 2 Enable—R/W. 0=Disable; 1=Enable.
2.5.5.2.
NMI Enable and Real-Time Clock Address Register
I/O Address:
Default Value:
Attribute:
070h
Bit[6:0]=undefined; Bit 7=1
Write Only
This port is shared with the real-time clock. Do not modify the contents of this register without considering the
effects on the state of the other bits. Reads and writes to this register address flow through to the ISA Bus.
Bit
Description
7
NMI Enable. 1=Disable; 0=Enable.
6:0 Real Time Clock Address. Used by the Real Time Clock on the Base I/O component to
address memory locations. Not used for NMI enabling/disabling.
2.6. System Power Management Registers
This section describes two power management registers—APMS and APMC Registers. These registers are
located in normal I/O space and must be accessed (via the PCI Bus) with 8-bit accesses.
2.6.1. APMC—ADVANCED POWER MANAGEMENT CONTROL PORT
I/O Address:
Default Value:
Attribute:
0B2h
00h
Read/Write
This register passes data (APM Commands) between the OS and the SMI handler. In addition, writes can
generate an SMI and reads can cause STPCLK# to be asserted. The PIIX/PIIX3 operation is not effected by
the data in this register.
Bit
Description
7:0
APM Control Port (APMC). Writes to this register store data in the APMC Register and reads
return the last data written. In addition, writes generate an SMI, if bit 7 of the SMIEN Register
and bit 0 of the SMICNTL Register are both is set to 1. Reads cause the STPCLK# signal to
be asserted, if bit 1 of the SMICNTL Register is set to 1. Reads do not generate an SMI.
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