82371FB Datasheet, PDF (31/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

E
82371FB (PIIX) AND 82371SB (PIIX3)
2.2. PCI Configuration Registers—PCI To ISA Bridge (Function 0)
2.2.1. VID—VENDOR IDENTIFICATION REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
00–01h
8086h
Read Only
The VID Register contains the vendor identification number. This register, along with the Device Identification
Register, uniquely identifies any PCI device. Writes to this register have no effect.
Bit
Description
15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel.
2.2.2. DID—DEVICE IDENTIFICATION REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
02–03h
122Eh
7000h
Read Only
(PIIX)
(PIIX3)
The DID Register contains the device identification number. This register, along with the VID Register, define
the PIIX. Writes to this register have no effect.
Bit
Description
15:0 Device Identification Number. This is a 16-bit value assigned to the PIIX.
2.2.3. PCICMD—COMMAND REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
04–05h
0007h
Read/Write
This 16-bit register provides basic control over the PIIX's ability to respond to PCI cycles.
Bit
15:10
9
8
7:5
4
3
Description
Reserved. Read as 0.
Fast Back-to-Back Enable. (Not Implemented) This bit is hardwired to 0.
PIIX: Reserved. Read as 0.
PIIX3: SERR# Enable (SERRE). 1=Enable. 0=Disable. When enabled (and bit 3=1 in the
DLC register), a delayed transaction timeout causes the PIIX3 to assert the SERR# signal.
The PCISTS register reports the status of the SERR# signal.
Reserved. Read as 0.
Postable Memory Write Enable. (Not Implemented) This bit is hardwired to 0.
Special Cycle Enable (SCE). 1=Enable, the PIIX/PIIX3 recognizes shutdown special cycle.
0=Disable, the PIIX/PIIX3 ignores all PCI Special Cycles.
31